EASY 6996M CPU Infineon Technologies, EASY 6996M CPU Datasheet - Page 70

• Manufacturer Part Number: EASY 6996M CPU
• Description: BOARD EVAL W/CPU ADM6996M
• Manufacturer: Infineon Technologies
• Series: Samurair

Specifications of EASY 6996M CPU

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: ADM6996M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Primary Attributes: -
• Other names: EASY6996MCPUIN

Figure 11
Note:
5. From the
6. Pin 51 (SPDTNP4) acts as DUPLEX LED for Port 4; in half duplex mode, it is collision LED for each port.
7. Pin 107 (DPHALFP4) used to indicate the speed status of Port 4.
8. Pin 92 (LNKFP4) used to indicate the link/activity status of Port 4.
3.3
The 100Base-X section of the device implements the following functional blocks:
100Base-X physical coding sub-layer (PCS)
100Base-X physical medium attachment (PMA)
100Base-X physical medium dependent (PMD)
The 10Base-T section of the device implements the following functional blocks:
10Base-T physical layer signaling (PLS)
10Base-T physical medium attachment (PMA)
The 100Base-X and 10Base-T sections share the following functional blocks:
Clock synthesizer module
MII Registers
IEEE 802.3u auto negotiation
The interfaces used for communication between PHY block and switch core is MII interface.
Auto MDIX function is supported. This function can be Enable/Disabled by the hardware pin.
The Digital approach for the integrated PHY of Samurai-6M/6MX (ADM6996M/MX) has been adopted.
Data Sheet
be operating in PCS mode MII. So it doesn’t matter the value on P4_BUSMD[1:0] (pin 105 and pin 106) and
we only pull high the CFG0 or make it floating (due to it has internally pull high) is ok.
PCS to MAC MII connection
10/100M PHY Block
CFG0
pin description, we know it needs to set {CFG0, P4_BUSMD[1:0]} as 1xx
70
Revision 1.4, 2006-03-24
Function Description
Samurai-6M/MX
B
ADM6996M/MX
to configure Port4