EASY 6996M CPU Infineon Technologies, EASY 6996M CPU Datasheet - Page 44

• Manufacturer Part Number: EASY 6996M CPU
• Description: BOARD EVAL W/CPU ADM6996M
• Manufacturer: Infineon Technologies
• Series: Samurair

Specifications of EASY 6996M CPU

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: ADM6996M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Primary Attributes: -
• Other names: EASY6996MCPUIN

Table 22
Queue
Queue 0
Queue 1
Queue 2
Queue 3
3.1.15.1
The system PRI is determined in the order as follows:
1. (DA+FID) was found in the learning table, then LRN_PRI field (when LRN_PRIEN is set) in this entry indicates
2. Port PRI in basic control register indicates the priority queue, when Port_PRIEN is enabled on that port.
3. The user priority field in the tag header is used for a tagged packet (“Input Force No Tag” doesn’t effect
4. For IP packets with no tag header, IP PRI is used when “Service Priority” (see 001F
5. If the packet matches the TCP/UDP filters, the PRI associated with this filter indicates the priority queue when
3.1.15.2
Table 23
Packets Identified by Samurai-
6M/6MX (ADM6996M/MX)
BPDU/SLOW/PAE/RESER_R0/
RESER_R1/GXRP/RESER_R2/
RESER_R3
ARP/RARP
Data Sheet
the priority queue.
Samurai-6M/6MX (ADM6996M/MX) to extract the PRI in the tag header), when “VLAN Priority” is enabled. The
user priority in the tag header is a 3 bits field, Samurai-6M/6MX (ADM6996M/MX) uses “VLAN Priority MAP”
to map the priority queue.
tagged packet with IP header, we can set “IP over VLAN” (see basic control registers) bit to 1 to force using IP
PRI. Three kinds of IP PRI are available.
a) For IPV6 packets with IP Version = 6
b) For IPV4 packets with IP Version = 4
c) If “TOS Using” (see 000A
“TCP/UDP PRIEN” is set to 1 (see 0098
PRI when there is a match.
used to map the priority queue by the service mapping registers.
to map the priority queue by the TOS Priority Map register.
the most significant 6 bits of the TOS field to map the priority queue by the service mapping registers.
Priority Queue
System PRI
Queue Assigned
Queue Assigned
H
) is disabled, even for IPV4 packets, Samurai-6M/6MX (ADM6996M/MX) uses
Weight = “Queue 1 Weight” bits in 0025
Weight = “Queue 2 Weight” bits in 0026
Weight = “Queue 3 Weight” bits in 0027
Weight
Weight = 1
1. The PRI field with PRI_Valid = 1 in the Special TAG indicates the priority
The Order of Priority Assigned
1. The PRI field with PRI_Valid = 1 in the Special TAG indicates the priority
2. If (DA+FID) matches an entry in the learning table, then LRN_PRI field with
3. Use PRI in 003D
2. Use PRI in 000D
3. Use System PRI.
queue.
LRN_PRIEN enabled in this entry indicates the priority queue.
queue.
H
H
H
, the most significant 3 bits of the TOS field in the IPV4 header is used
, the most significant 6 bits of the traffic class in the IPV6 header is
). Users could enable “TCPUDP over IP” to force using the TCPUDP
H
H
44
to indicate the queue the frame was switched.
to indicate the priority queue when enabled.
H
H
H
Revision 1.4, 2006-03-24
H
) is enabled. Even for a
Function Description
Samurai-6M/MX
ADM6996M/MX