EASY 6996M CPU Infineon Technologies, EASY 6996M CPU Datasheet - Page 77
EASY 6996M CPU
Manufacturer Part Number
EASY 6996M CPU
Description
BOARD EVAL W/CPU ADM6996M
Manufacturer
Infineon Technologies
Series
Samurair
Datasheet
1.EASY_6996M_CPU.pdf
(216 pages)
Specifications of EASY 6996M CPU
Main Purpose
Interface, Ethernet
Embedded
No
Utilized Ic / Part
ADM6996M
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Primary Attributes
-
Other names
EASY6996MCPUIN
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Figure 15
3.4.3
The SMI consists of two pins, management data clock (EESK) and management data input/output (EDI). The
Samurai-6M/6MX (ADM6996M/MX) is designed to support an EESK frequency up to 25 MHz. The EDI pin is bi-
directional and may be shared with other devices. EECS pin is needed to pull low if EEPROM interface is also
used.
The EDI pin requires a 1.5 K pull-up which, during idle and turnaround periods, will pull EDI to a logic one state.
Samurai-6M/6MX (ADM6996M/MX) requires a single initialization sequence of 32 bits of preamble following
power-up/hardware reset. The first 32 bits are preamble consisting of 32 contiguous logic one bits on EDI and 32
corresponding cycles on EESK. Following preamble is the start-of-frame field indicated by a <01
next field signals the operation code (OP): <10
indicates write to management register operation. The next field is the management register address. It is 10 bits
wide and the most significant bit is transferred first.
During Read operation, a 2-bit turn around (TA) time spacing between the register address field and data field is
provided for the EDI to avoid contention. Following the turnaround time, a 16-bit data stream is read from or written
into the management registers of the Samurai-6M/6MX (ADM6996M/MX).
(A) Preamble Suppression
The SMI of Samurai-6M/6MX (ADM6996M/MX) supports a preamble suppression mode. The Samurai-6M/6MX
(ADM6996M/MX) requires a single initialization sequence of 32 bits of preamble following power-up/hardware
reset. This requirement is generally met by pulling-up the resistor of EDI While the Samurai-6M/6MX
(ADM6996M/MX) will respond to management accesses without preamble, a minimum of one idle bit between
management transactions is required.
Data Sheet
Timing Diagram of RC, EECS and EESK (without EEPROM)
SMI Interface
B
> indicates read from management register operation, and <01
77
Revision 1.4, 2006-03-24
Function Description
Samurai-6M/MX
ADM6996M/MX
B
> pattern. The
B
>
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