EASY 6996M CPU Infineon Technologies, EASY 6996M CPU Datasheet - Page 27

• Manufacturer Part Number: EASY 6996M CPU
• Description: BOARD EVAL W/CPU ADM6996M
• Manufacturer: Infineon Technologies
• Series: Samurair

Specifications of EASY 6996M CPU

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: ADM6996M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Primary Attributes: -
• Other names: EASY6996MCPUIN

Table 3
Ball No.
86
69
65
40
44
85
119
120
121
127
Data Sheet
IO Signals (cont’d)
Name
CFG0
WAIT_INIT
INT_N
MDIO
MDC
CKO25M
RC
XI
XO
RTX
Pin
Type
I
I
O
I/O
I
O
I
AI
AO
AI
Buffer
Type
PU,
LVTTL
PD,
LVTTL
OD,8 mA Interrupt
8 mA,
PD,
LVTTL
PD, ST
8 mA,
PD,
LVTTL
ST
ANA
ANA
ANA
Function
Configuration 0
Combined with
6M/6MX (ADM6996M/MX) provides 3 bus type for port 4.
{CFG0, P4_BUSMD[1:0]}, Bus Mode of Port 4
0_00
0_01
1_XX
Wait Initialization
This pin will be used to pause all activities after power up
until EEPROM is loaded successfully or CPU initialization
is done..
0
1
Active low interrupt signal to indicate the status change in
the interrupt status register. Interrupt signal will keep active
low until host read the status of ISR register.
0
1
Management Data
MDIO transfers management data in and out of the device
synchronous to MDC.
Management Data Reference Clock
A non-continuous clock input for management usage.
Samurai-6M/6MX (ADM6996M/MX) will use this clock to
sample data input on MDIO and drive data onto MDIO
according to rising edge of this clock.
25M Clock Output
Free Running 25M Clock output (Even during power on
reset)
RC Input For Power On Reset
This pin is sampled by using the 25 MHz free running clock
signal which gets the input from
active reset signal, RESETL. See
Reset
25MHz Crystal /Oscillator Input
25MHz Crystal or Oscillator Input. Variation is limited to +/-
50ppm.
25MHz Crystal Output
When connected to oscillator, this pin should be left
unconnected.
Constant Voltage Reference
External 1.0 k 1% resistor connection to ground.
B
B
B
B
27
B
B
B
initialization is done.
PHY Interface
MAC MII
for the timing requirements.
pause until loading EEPROM is done.
pause until EEPROM successfully loaded or CPU
Interrupt
Not interrupt
PCS MII
P4_BUSMD0
and P4_BUSMD1, Samurai-
XI
Chapter 5.3.2 Power On
Revision 1.4, 2006-03-24
to generate the low-
Interface Description
Samurai-6M/MX
ADM6996M/MX