DTMFDECODER-RD Silicon Laboratories Inc, DTMFDECODER-RD Datasheet - Page 83

• Manufacturer Part Number: DTMFDECODER-RD
• Description: KIT REF DESIGN DTMF DECODER
• Manufacturer: Silicon Laboratories Inc

Specifications of DTMFDECODER-RD

• Mfg Application Notes: DTMF Decoder Ref Design AppNote
• Main Purpose: Telecom, DTMF Decoder
• Embedded: No
• Utilized Ic / Part: C8051F300
• Primary Attributes: 8kHz Sampling Rate ADC
• Secondary Attributes: 16 Goertzel Filters
• Processor To Be Evaluated: C8051F300
• Interface Type: RS-232
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 336-1283

9.
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
•
•
•
•
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled dur-
ing and after the reset. For V
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. Refer to
the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its clock
source
Once the system clock source is stable, program execution begins at location 0x0000.
XTAL1
XTAL2
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
Reset Sources
(Section “16.3. Watchdog Timer Mode” on page 164
Oscillator
Oscillator
External
Internal
Drive
P0.x
P0.y
Section “11. Oscillators” on page 97
Clock Select
System
Clock
DD
Monitor and power-on resets, the RST pin is driven low until the device
Comparator 0
Figure 9.1. Reset Sources
+
-
Detector
Missing
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
C0RSEF
CIP-51
Core
Handler
VDD
WDT
PCA
EN
Rev. 2.9
Supply
Monitor
+
-
System Reset
Enable
Power On
for information on selecting and configuring
Reset
C8051F300/1/2/3/4/5
details the use of the Watchdog Timer).
(Software Reset)
SWRSF
'0'
Operation
FLASH
Illegal
(wired-OR)
Reset
Funnel
/RST
83