DTMFDECODER-RD Silicon Laboratories Inc, DTMFDECODER-RD Datasheet - Page 41
![KIT REF DESIGN DTMF DECODER](/photos/9/6/90685/dtmfdecoder-rd_sml.jpg)
DTMFDECODER-RD
Manufacturer Part Number
DTMFDECODER-RD
Description
KIT REF DESIGN DTMF DECODER
Manufacturer
Silicon Laboratories Inc
Specifications of DTMFDECODER-RD
Mfg Application Notes
DTMF Decoder Ref Design AppNote
Main Purpose
Telecom, DTMF Decoder
Embedded
No
Utilized Ic / Part
C8051F300
Primary Attributes
8kHz Sampling Rate ADC
Secondary Attributes
16 Goertzel Filters
Processor To Be Evaluated
C8051F300
Interface Type
RS-232
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
336-1283
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5.3.3. Settling Time Requirements
When the ADC0 input configuration is changed (i.e., a different AMUX0 or PGA selection is made), a mini-
mum tracking time is required before an accurate conversion can be performed. This tracking time is deter-
mined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the
accuracy required for the conversion. Note that in low-power tracking mode, three SAR clocks are used for
tracking at the start of every conversion. For most applications, these three SAR clocks will meet the mini-
mum tracking time requirements.
Figure 5.5 shows the equivalent ADC0 input circuits for both Differential and Single-ended modes. Notice
that the equivalent time constant for both input circuits is the same. The required ADC0 settling time for a
given settling accuracy (SA) may be approximated by Equation 5.1. When measuring the Temperature
Sensor output or V
settling time (track/hold time) requirements.
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R
n is the ADC resolution in bits (8).
TOTAL
is the sum of the AMUX0 resistance and any external source resistance.
P0.x
P0.y
RC
Differential Mode
MUX Select
MUX Select
Input
DD
= R
Equation 5.1. ADC0 Settling Time Requirements
with respect to GND, R
MUX
R
R
Figure 5.5. ADC0 Equivalent Input Circuits
* C
MUX
MUX
SAMPLE
= 5k
= 5k
Note: When the PGA gain is set to 0.5, C
t
=
C
C
ln
SAMPLE
SAMPLE
------ -
SA
2
= 5pF
= 5pF
n
TOTAL
Rev. 2.9
R
TOTAL
reduces to R
C
P0.x
SAMPLE
C8051F300/1/2/3/4/5
Single-Ended Mode
SAMPLE
RC
MUX
MUX Select
Input
= R
= 3pF
. See Table 5.1 for ADC0 minimum
MUX
R
* C
MUX
SAMPLE
= 5k
C
SAMPLE
= 5pF
41
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