DTMFDECODER-RD Silicon Laboratories Inc, DTMFDECODER-RD Datasheet - Page 144

• Manufacturer Part Number: DTMFDECODER-RD
• Description: KIT REF DESIGN DTMF DECODER
• Manufacturer: Silicon Laboratories Inc

Specifications of DTMFDECODER-RD

• Mfg Application Notes: DTMF Decoder Ref Design AppNote
• Main Purpose: Telecom, DTMF Decoder
• Embedded: No
• Utilized Ic / Part: C8051F300
• Primary Attributes: 8kHz Sampling Rate ADC
• Secondary Attributes: 16 Goertzel Filters
• Processor To Be Evaluated: C8051F300
• Interface Type: RS-232
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 336-1283

C8051F300/1/2/3/4/5
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to
“12.1. Priority Crossbar Decoder” on page 104
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see SFR Definition 15.3).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
/INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 8.11). Setting GATE0 to ‘1’
allows the timer to be controlled by the external input signal /INT0 (see
Descriptions” on page
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal /INT1 is used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 8.11).
144
/INT0
T0
Crossbar
Pre-scaled Clock
SYSCLK
IN0PL
GATE0
75), facilitating pulse width measurements.
*Note: X = Don't Care
XOR
Figure 15.1. T0 Mode 0 Block Diagram
TR0
0
1
1
1
TR0
0
1
M
T
H
2
GATE0
CKCON
M
T
2
L
X*
M
T
1
0
1
1
0
1
M
T
0
C
S
A
1
S
C
A
Rev. 2.9
0
for information on selecting and configuring external I/O
G
A
T
E
1
/INT0
C
T
1
/
X*
X*
0
1
M
T
1
1
TMOD
M
T
1
0
TCLK
G
A
T
E
0
C
T
0
/
M
T
0
1
Counter/Timer
M
T
0
0
(5 bits)
TL0
Disabled
Disabled
Enabled
Enabled
N
P
1
L
I
N
S
1
L
2
I
Section “8.3.5. Interrupt Register
IT01CF
N
1
S
L
1
I
N
S
1
L
0
I
N
0
P
L
(8 bits)
I
TH0
N
S
0
L
2
I
N
0
S
L
1
I
N
S
0
L
0
I
TR1
TR0
TF1
TF0
IE1
IE0
IT1
IT0
Section
Interrupt