DTMFDECODER-RD Silicon Laboratories Inc, DTMFDECODER-RD Datasheet
DTMFDECODER-RD
Specifications of DTMFDECODER-RD
Related parts for DTMFDECODER-RD
DTMFDECODER-RD Summary of contents
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Analog Peripherals - 8-Bit ADC ('F300/2 only 500 ksps • external inputs • Programmable amplifier gains & 0.5 • VREF from external pin or V • Built-in temperature sensor • External ...
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C8051F300/1/2/3/4 OTES 2 Rev. 2.9 ...
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Table of Contents 1. System Overview.................................................................................................... 13 1.1. CIP-51™ Microcontroller Core.......................................................................... 16 1.1.1. Fully 8051 Compatible.............................................................................. 16 1.1.2. Improved Throughput ............................................................................... 16 1.1.3. Additional Features .................................................................................. 17 1.2. On-Chip Memory............................................................................................... 18 1.3. On-Chip Debug Circuitry................................................................................... 19 1.4. Programmable Digital I/O ...
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C8051F300/1/2/3/4/5 8.3.4. Interrupt Latency ...................................................................................... 73 8.3.5. Interrupt Register Descriptions................................................................. 75 8.4. Power Management Modes .............................................................................. 80 8.4.1. Idle Mode.................................................................................................. 80 8.4.2. Stop Mode ................................................................................................ 81 9. Reset Sources......................................................................................................... 83 9.1. Power-On Reset ............................................................................................... 84 9.2. Power-Fail Reset/VDD Monitor......................................................................... 84 ...
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SMBus............................................................................................ 115 13.4.1.SMBus Configuration Register............................................................... 116 13.4.2.SMB0CN Control Register ..................................................................... 119 13.4.3.Data Register ......................................................................................... 122 13.5.SMBus Transfer Modes.................................................................................. 123 13.5.1.Master Transmitter Mode ....................................................................... 123 13.5.2.Master Receiver Mode ........................................................................... 124 13.5.3.Slave Receiver Mode ............................................................................. 125 13.5.4.Slave Transmitter Mode ......................................................................... ...
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C8051F300/1/2/3/4 OTES 6 Rev. 2.9 ...
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List of Figures 1. System Overview Figure 1.1. C8051F300/2 Block Diagram ................................................................. 15 Figure 1.2. C8051F301/3/4/5 Block Diagram ........................................................... 15 Figure 1.3. Comparison of Peak MCU Execution Speeds ....................................... 16 Figure 1.4. On-Chip Clock and Reset ...................................................................... 17 Figure 1.5. ...
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C8051F300/1/2/3/4/5 10. Flash Memory Figure 10.1. Flash Program Memory Map................................................................ 91 11. Oscillators Figure 11.1. Oscillator Diagram................................................................................ 97 Figure 11.2. 32.768 kHz External Crystal Example................................................ 101 12. Port Input/Output Figure 12.1. Port I/O Functional Block Diagram ..................................................... 103 Figure 12.2. ...
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List of Tables 1. System Overview Table 1.1. Product Selection Guide ......................................................................... 14 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings .................................................................... 24 3. Global Electrical Characteristics Table 3.1. Global Electrical Characteristics ............................................................. 25 4. Pinout and Package Definitions ...
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C8051F300/1/2/3/4/5 Table 14.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator ......................................... 139 Table 14.4. Timer Settings for Standard Baud Rates Using an External 18.432 MHz Oscillator ........................................... 140 Table 14.5. Timer Settings for ...
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List of Registers SFR Definition 5.1. AMX0SL: AMUX0 Channel Select (C8051F300/ SFR Definition 5.2. ADC0CF: ADC0 Configuration (C8051F300/ ...
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C8051F300/1/2/3/4/5 SFR Definition 15.4. TL0: Timer 0 Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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System Overview C8051F300/1/2/3/4/5 devices are fully integrated mixed-signal system-on-a-chip MCUs. Highlighted fea- tures are listed below. Refer to Table 1.1 on page 14 for specific product feature selection. • High-speed pipelined 8051-compatible microcontroller core ( MIPS) • ...
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C8051F300/1/2/3/4/5 Table 1.1. Product Selection Guide C8051F300- C8051F300- C8051F301- C8051F301- C8051F302- C8051F302- C8051F303- C8051F303- C8051F304-GM 25 ...
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Analog/Digital VDD Power GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator XTAL2 Circuit System Clock Precision Internal Oscillator Figure 1.1. C8051F300/2 Block Diagram Analog/Digital VDD Power GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External ...
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C8051F300/1/2/3/4/5 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F300/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. ...
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Additional Features The C8051F300/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and periph- erals to improve performance and ease of use in end applications. The extended interrupt handler provides 12 interrupt sources into the CIP-51 (as ...
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C8051F300/1/2/3/4/5 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and ...
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On-Chip Debug Circuitry The C8051F300/1/2/3/4/5 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non-intrusive, full-speed, in-circuit debugging of the production part installed in the end application. Silicon Labs' debugging system supports inspection and modification of memory ...
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C8051F300/1/2/3/4/5 Perhaps the most unique Port I/O enhancement is the Digital Crossbar. This is essentially a digital switch- ing network that allows mapping of internal digital system resources to Port I/O pins (See Figure 1.7). On- chip counter/timers, serial buses, ...
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Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the three 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three pro- grammable capture/compare modules. The PCA clock ...
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C8051F300/1/2/3/4/5 1.7. 8-Bit Analog to Digital Converter (C8051F300/2 Only) The C8051F300/2 includes an on-chip 8-bit SAR ADC with a 10-channel differential input multiplexer and programmable gain amplifier. With a maximum throughput of 500 ksps, the ADC offers true 8-bit accuracy ...
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Comparator C8051F300/1/2/3/4/5 devices include an on-chip voltage comparator that is enabled/disabled and config- ured via user software. All Port I/O pins may be configurated as comparator inputs. Two comparator out- puts may be routed to a Port pin if ...
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C8051F300/1/2/3/4/5 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings* Parameter Ambient temperature under bias Storage Temperature Voltage on any Port I/O Pin or RST with respect to GND Voltage on V with respect to GND DD Maximum Total current ...
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Global Electrical Characteristics Table 3.1. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Digital Supply Voltage Digital Supply RAM Data Retention Voltage SYSCLK (System Clock) (Note 2) T (SYSCLK High Time) SYSH ...
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C8051F300/1/2/3/4/5 Table 3.1. Global Electrical Characteristics (Continued) –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter I Supply Sensitivity (Note MHz MHz I Frequency Sensitivity (Note ...
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Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F300/1/2/3/4/5 Name Pin Pin F300/1/2/3/4/5 F300/1/2/3/4 VREF / 1 5 P0.0 P0 XTAL1 / 4 8 P0.2 XTAL2 / 5 10 ...
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C8051F300/1/2/3/4/5 VREF / P0.0 P0.1 VDD XTAL1 / P0.2 XTAL2 / P0.3 Figure 4.1. QFN-11 Pinout Diagram (Top View) 28 GND Rev. 2.9 C2D / P0.7 P0.6 / CNVSTR C2CK / /RST P0.5 P0.4 ...
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Figure 4.2. QFN-11 Package Drawing Table 4.2. QFN-11 Package Dimensions Dimension Min Nom A 0.80 0.90 A1 0.03 0.07 A3 0.25 REF b 0.18 0.25 D 3.00 BSC. D2 1.30 1.35 e 0.50 BSC. Notes: 1. All dimensions shown are ...
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C8051F300/1/2/3/4/5 0.10 mm 0.35 mm 0.50 mm 0. Figure 4.3. Typical QFN-11 Solder Paste Mask 0.50 mm 0.35 mm 0. 0.60 mm 0. ...
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Figure 4.4. Typical QFN-11 Landing Diagram Table 4.3. QFN-11 Landing Diagram Dimensions Dimension Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is ...
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C8051F300/1/2/3/4/5 P0.6 1 C2D/P0.7 2 GND 3 N/C 4 P0.0 5 P0.1 6 VDD 7 Figure 4.5. SOIC-14 Pinout Diagram (Top View) 32 TOP VIEW Rev. 2.9 C2CK/RST P0.5 P0.4 N/C P0.3 N/C ...
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Figure 4.6. SOIC-14 Package Drawing Table 4.4. SOIC-14 Package Dimensions Dimension Min Max 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.17 0.25 D 8.65 BSC E 6.00 BSC E1 3.90 BSC e 1.27 BSC Notes: ...
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C8051F300/1/2/3/4/5 Figure 4.7. SOIC-14 PCB Land Pattern Table 4.5. SOIC-14 PCB Land Pattern Dimensions Dimension Min Max 5.30 5.40 1.27 BSC 0.50 0.60 1.45 1.55 Rev. 2.9 ...
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ADC0 (8-Bit ADC, C8051F300/2) The ADC0 subsystem for the C8051F300/2 consists of two analog multiplexers (referred to collectively as AMUX0) with 11 total input selections, a differential programmable gain amplifier (PGA), and a 500 ksps, 8- bit successive-approximation-register ADC ...
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C8051F300/1/2/3/4/5 5.1. Analog Multiplexer and PGA The analog multiplexers (AMUX0) select the positive and negative inputs to the PGA, allowing any Port pin to be measured relative to any other Port pin or GND. Additionally, the on-chip temperature sensor or ...
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Figure 5.2. Typical Temperature Sensor Transfer Function The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature mea- surements (see Table 5.1 for linearity specifications). For absolute temperature measurements, ...
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C8051F300/1/2/3/4/5 5.00 4.00 3.00 2.00 1.00 0.00 -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2. 40.00 0.00 20.00 Temperature (degrees C) Rev. 2.9 5.00 4.00 3.00 2.00 1.00 ...
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Modes of Operation ADC0 has a maximum conversion speed of 500 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC + ...
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C8051F300/1/2/3/4/5 5.3.2. Tracking Modes According to Table 5.1 on page 47, each ADC0 conversion must be preceded by a minimum tracking time for the converted result to be accurate. The AD0TM bit in register ADC0CN controls the ADC0 track-and- hold ...
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Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 or PGA selection is made), a mini- mum tracking time is required before an accurate conversion can be performed. This tracking time is deter- mined ...
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C8051F300/1/2/3/4/5 SFR Definition 5.1. AMX0SL: AMUX0 Channel Select (C8051F300/2) R/W R/W R/W AMX0N3 AMX0N2 AMX0N1 AMX0N0 AMX0P3 Bit7 Bit6 Bit5 Bits7–4: AMX0N3–0: AMUX0 Negative Input Selection. Note that when GND is selected as the Negative Input, ADC0 operates in Single-ended ...
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SFR Definition 5.2. ADC0CF: ADC0 Configuration (C8051F300/2) R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 AD0SC1 Bit7 Bit6 Bit5 Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers ...
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C8051F300/1/2/3/4/5 SFR Definition 5.4. ADC0CN: ADC0 Control (C8051F300/2) R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 ...
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Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an inter- rupt-driven system, saving code space and ...
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C8051F300/1/2/3/4/5 5.4.2. Window Detector In Differential Mode Figure 5.7 shows two example window comparisons for differential mode, with ADC0LT = 0x10 (+16d) and ADC0GT = 0xFF (–1d). Notice that in Differential mode, the codes vary from –VREF to VREF x ...
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Table 5.1. ADC0 Electrical Characteristics V = 3.0 V, VREF = 2.40 V (REFSL = 0), PGA Gain = 1, –40 to +85 °C unless otherwise specified. DD Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Offset Error ...
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C8051F300/1/2/3/4 OTES 48 Rev. 2.9 ...
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Voltage Reference (C8051F300/2) The voltage reference MUX on C8051F300/2 devices is configurable to use an externally connected volt- age reference or the power supply voltage, V register (REF0CN) selects the reference source. For an external source, REFSL should be ...
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C8051F300/1/2/3/4/5 SFR Definition 6.1. R/W R/W R/W — — — Bit7 Bit6 Bit5 Bits7–3: UNUSED. Read = 00000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF input ...
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Comparator0 C8051F300/1/2/3/4/5 devices include an on-chip programmable voltage comparator, which is shown in Figure 7.1. Comparator0 offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous ...
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C8051F300/1/2/3/4/5 The output of Comparator0 can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, the Comparator0 output is available asynchronous or synchronous to the system clock; the ...
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Comparator0 interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt enable and priority control, see is set to logic 1 upon a Comparator0 falling-edge interrupt, and the CP0RIF flag is set to logic 1 upon the ...
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C8051F300/1/2/3/4/5 SFR Definition 7.2. R/W R/W R/W — — CMX0N1 CMX0N0 Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bits6–4: CMX0N1–CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is used as the ...
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Table 7.1. Comparator0 Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise specified. DD Parameter Response Time: CP0+ – CP0– = 100 mV Mode 0, Vcm* = 1.5 V CP0+ – CP0– = –100 mV Response Time: ...
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C8051F300/1/2/3/4 OTES 56 Rev. 2.9 ...
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CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset ...
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C8051F300/1/2/3/4/5 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to execute, ...
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CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. 8.1.2. MOVX Instruction and Program Memory The MOVX instruction is typically used to access external data memory (Note: the C8051F300/1/2/3/4/5 does ...
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C8051F300/1/2/3/4/5 Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic ANL direct, A AND A to direct byte ANL direct, #data AND immediate to direct byte ORL Register to A ORL A, direct OR direct byte to A ...
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Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic MOVC A, @A+PC Move code byte relative MOVX A, @Ri Move external data (8-bit address MOVX @Ri, A Move A to external data (8-bit address) MOVX A, ...
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C8051F300/1/2/3/4/5 Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic JNZ rel Jump if A does not equal zero CJNE A, direct, rel Compare direct byte to A and jump if not equal CJNE A, #data, rel Compare immediate to A ...
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Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but ...
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C8051F300/1/2/3/4/5 8.2.2. Data Memory The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem- ory. ...
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Bit Addressable Locations In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 ...
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C8051F300/1/2/3/4/5 Table 8.2. Special Function Register (SFR) Memory Map F8 CPT0CN PCA0L F0 B P0MDIN E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 E0 ACC XBR0 D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 D0 PSW REF0CN C8 TMR2CN C0 SMB0CN SMB0CF B8 IP ...
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Table 8.3. Special Function Registers* (Continued) Register Address 0xB6 FLSCL Flash Scale 0xA8 IE Interrupt Enable 0xB8 IP Interrupt Priority 0xE4 IT01CF INT0/INT1 Configuration Register 0xB3 OSCICL Internal Oscillator Calibration 0xB2 OSCICN Internal Oscillator Control 0xB1 OSCXCN External Oscillator Control ...
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C8051F300/1/2/3/4/5 Table 8.3. Special Function Registers* (Continued) Register Address 0x8D TH1 Timer/Counter 1 High 0x8A TL0 Timer/Counter 0 Low 0x8B TL1 Timer/Counter 1 Low 0x89 TMOD Timer/Counter Mode 0xCB TMR2RLH Timer/Counter 2 Reload High 0xCA TMR2RLL Timer/Counter 2 Reload Low ...
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SFR Definition 8.2. R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: DPH: Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed Flash memory. SFR Definition 8.3. R/W R/W R/W ...
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C8051F300/1/2/3/4/5 SFR Definition 8.4. R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction cleared to logic ...
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SFR Definition 8.5. R/W R/W R/W ACC.7 ACC.6 ACC.5 ACC.4 Bit7 Bit6 Bit5 Bits7–0: ACC: Accumulator. This register is the accumulator for arithmetic operations. SFR Definition 8.6. R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7– Register. ...
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C8051F300/1/2/3/4/5 8.3. Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 12 interrupt sources with two prior- ity levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific ...
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External Interrupts The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active ...
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C8051F300/1/2/3/4/5 Table 8.4. Interrupt Summary Interrupt Interrupt Source Vector Reset 0x0000 External Interrupt 0 (/INT0) 0x0003 Timer 0 Overflow 0x000B External Interrupt 1 (/INT1) 0x0013 Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SMBus Interface 0x0033 ADC0 Window ...
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Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral ...
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C8051F300/1/2/3/4/5 SFR Definition 8.8. R/W R/W R/W — — PT2 Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 11b, Write = don't care. Bit5: PT2: Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer 2 interrupt. 0: ...
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SFR Definition 8.9. R/W R/W R/W — — ECP0R ECP0F Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b. Write = don’t care. Bit5: ECP0R: Enable Comparator0 (CP0) Rising Edge Interrupt. This bit sets the masking of the CP0 Rising Edge ...
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C8051F300/1/2/3/4/5 SFR Definition 8.10. R/W R/W R/W — — PCP0R Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 11b. Write = don’t care. Bit5: PCP0R: Comparator0 (CP0) Rising Interrupt Priority Control. This bit sets the priority of the CP0 rising-edge interrupt. ...
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SFR Definition 8.11. R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to SFR Definition 15.1 for INT0/1 edge- or level-sensitive interrupt selection. Bit7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: /INT1 input is active ...
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C8051F300/1/2/3/4/5 8.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter- rupts ...
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Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc- tion that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital periph- ...
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C8051F300/1/2/3/4 OTES 82 Rev. 2.9 ...
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Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to their ...
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C8051F300/1/2/3/4/5 9.1. Power-On Reset During powerup, the device is held in a reset state and the RST pin is driven low until additional delay occurs before the device is released from reset; the delay decreases as ...
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RSTSRC. See Figure 9.2 for V after a V monitor reset. See Table 9.2 for electrical characteristics of the V DD Important Note: Enabling the V monitor will immediately generate a system reset. The device will then ...
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C8051F300/1/2/3/4/5 9.7. Flash Error Reset If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This may occur due to any of the following: • A Flash write or erase is attempted above user ...
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SFR Definition 9. R/W — FERROR C0RSEF SWRSF WDTRSF MCDRSF Bit7 Bit6 Bit5 (Note: Do not use read-modify-write operations (ORL, ANL) on this register) Bit7: UNUSED. Read = 0. Write = don’t care. Bit6: FERROR: Flash Error Indicator. ...
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C8051F300/1/2/3/4 OTES 88 Rev. 2.9 ...
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Flash Memory On-chip, reprogrammable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by soft- ware using the MOVX ...
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C8051F300/1/2/3/4/5 10.1.3. Flash Write Procedure Flash bytes are programmed by software with the following sequence: Step 1. Disable interrupts (recommended). Step 2. Erase the 512-byte Flash page containing the target location, as described in 10.1.2. Step 3. Set the PSWE ...
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Table 10.2. Security Byte Decoding Bits 7–4 Write Lock: Clearing any of these bits to logic 0 prevents all Flash memory from being written or page-erased across the C2 interface 3–0 Read/Write Lock: Clearing any of these bits to logic ...
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C8051F300/1/2/3/4/5 Accessing Flash from user firmware executing from an unlocked page: 1. Any unlocked page except the page containing the Lock Byte may be read, written, or erased. 2. Locked pages cannot be read, written, or erased. An erase attempt ...
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SFR Definition 10.2. R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: FLKEY: Flash Lock and Key Register Write: This register must be written to before Flash writes or erases can be performed. Flash remains locked until this register is written to ...
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C8051F300/1/2/3/4/5 10.4. Flash Write and Erase Guidelines Any system which contains routines which write or erase Flash memory from software involves some risk that the write or erase routines will execute unintentionally if the CPU is operating outside its specified ...
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Flash operation has been completed and interrupts have been re-enabled by software. 10. Make certain that the Flash write and erase pointer variables are not located in XRAM. See your compiler documentation for instructions ...
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C8051F300/1/2/3/4 OTES 96 Rev. 2.9 ...
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Oscillators C8051F300/1/2/3/4/5 devices include a programmable internal oscillator and an external oscillator drive circuit. The internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL reg- isters, as shown in Figure 11.1. The system clock can be ...
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C8051F300/1/2/3/4/5 SFR Definition 11.1. R/W R/W R/W — Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0. Write = don’t care. Bits 6–0: OSCICL: Internal Oscillator Calibration Register. This register calibrates the internal oscillator period. The reset value for OSCICL defines ...
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Table 11.1. Internal Oscillator Electrical Characteristics –40 to +85 °C unless otherwise specified Parameter Calibrated Internal Oscillator Frequency Uncalibrated Internal Oscillator Frequency Internal Oscillator Supply Current (from 11.2. External Oscillator Drive Circuit The external oscillator circuit may ...
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C8051F300/1/2/3/4/5 SFR Definition 11.3. OSCXCN: External Oscillator Control R R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: ...
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External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 11.1, Option 1. The External Oscillator Frequency Control value (XFCN) should ...
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C8051F300/1/2/3/4/5 11.5. External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 11.1, Option 2. The capacitor should be no greater than 100 pF; ...
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Port Input/Output Digital and analog resources are available through a byte-wide digital I/O Port, Port0. Each of the Port pins can be defined as general-purpose I/O (GPIO), analog input, or assigned to one of the internal digital resources as ...
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C8051F300/1/2/3/4/5 12.1. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 12.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least significant unassigned Port pin is assigned to that ...
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SF Signals VREF PIN I TX0 RX0 SDA SCL CP0 CP0A SYSCLK CEX0 CEX1 CEX2 ECI Port pin potentially available to peripheral Port pin skipped by CrossBar SF Signals Special Function Signals are not ...
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C8051F300/1/2/3/4/5 12.2. Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port0 Input Mode register (P0MDIN). Step 2. Select the output mode (open-drain ...
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SFR Definition 12.1. XBR0: Port I/O Crossbar Register 0 R/W R/W R/W — XSKP6 XSKP5 XSKP4 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0b; Write = don’t care. Bits6–0: XSKP[6:0]: Crossbar Skip Enable Bits These bits select Port pins to ...
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C8051F300/1/2/3/4/5 SFR Definition 12.3. XBR2: Port I/O Crossbar Register 2 R/W R/W R/W WEAKPUD XBARE — Bit7 Bit6 Bit5 Bit7: WEAKPUD: Port I/O Weak Pull-up Disable. 0: Weak Pull-ups enabled (except for Ports whose I/O are configured as push-pull). 1: ...
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SFR Definition 12.4. P0: Port0 Register R/W R/W R/W P0.7 P0.6 P0.5 Bit7 Bit6 Bit5 Bits7–0: P0.[7:0] Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers 0: Logic Low Output. 1: Logic High Output (open-drain if ...
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C8051F300/1/2/3/4/5 SFR Definition 12.6. P0MDOUT: Port0 Output Mode R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in regis- ter P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding ...
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SMBus The SMBus I/O interface is a two-wire bidirectional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I the interface by the system controller are byte oriented with the ...
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C8051F300/1/2/3/4/5 13.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The I C-Bus and How to Use It (including specifications), Philips Semiconductor The I C-Bus Specification ...
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The direction bit (R/W) occupies the least significant bit position of the address byte. The direction bit is set to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. All transactions are ...
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C8051F300/1/2/3/4/5 13.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster ...
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Using the SMBus The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con- trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides the following application-independent ...
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C8051F300/1/2/3/4/5 13.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the ...
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Timer Source Overflows SCL T Low Figure 13.4. Typical SMBus SCL Generation Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA setup time defines the absolute minimum time that SDA is ...
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C8051F300/1/2/3/4/5 SFR Definition 13.1. SMB0CF: SMBus Clock/Configuration R/W R/W R ENSMB INH BUSY Bit7 Bit6 Bit5 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly mon- itors the SDA and SCL pins. 0: SMBus ...
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SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 13.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to ...
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C8051F300/1/2/3/4/5 SFR Definition 13. R/W MASTER TXMODE STA Bit7 Bit6 Bit5 Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: SMBus operating in ...
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Table 13.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When: • A START is generated. MASTER • START is generated. TXMODE • The SMBus interface enters transmitter mode (after SMB0DAT is written before the start of an ...
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C8051F300/1/2/3/4/5 13.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is ...
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SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. ...
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C8051F300/1/2/3/4/5 13.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the ...
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Slave Receiver Mode Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and ...
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C8051F300/1/2/3/4/5 13.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START ...
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SMBus Status Decoding The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the shown response ...
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C8051F300/1/2/3/4/5 Table 13.4. SMBus Status Decoding (Continued) Values Read Current SMbus State 1000 master data byte was received; ACK requested. 0100 slave byte was transmitted; NACK received slave ...
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Table 13.4. SMBus Status Decoding (Continued) Values Read Current SMbus State 0010 slave address was received; ACK requested Lost arbitration as master; slave address received; ACK requested. 0010 Lost arbitration ...
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C8051F300/1/2/3/4 OTES 130 Rev. 2.9 ...
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UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “14.1. ...
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C8051F300/1/2/3/4/5 14.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer ...
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Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below. Figure 14.3. UART Interconnect Diagram 14.2.1. 8-Bit UART 8-Bit UART ...
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C8051F300/1/2/3/4/5 14.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit ...
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Multiprocessor Communications 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it ...
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C8051F300/1/2/3/4/5 SFR Definition 14.1. R/W R/W R/W S0MODE — MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: Mode 0: 8-bit UART with Variable Baud Rate 1: Mode 1: 9-bit ...
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SFR Definition 14.2. R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: SBUF0[7:0]: Serial Data Buffer Bits 7–0 (MSB-LSB) This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to ...
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C8051F300/1/2/3/4/5 Table 14.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz Target Baud Rate % Error Baud Rate (bps) 230400 –0.32% 115200 –0.32% 57600 0.15% 28800 –0.32% 14400 0.15% 9600 –0.32% 2400 –0.32% 1200 0.15% Notes: 1. ...
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Table 14.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Target Baud Rate % Error Baud Rate (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% 115200 ...
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C8051F300/1/2/3/4/5 Table 14.4. Timer Settings for Standard Baud Rates Using an External 18.432 MHz Target Baud Rate % Error Baud Rate (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% ...
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Table 14.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz Target Baud Rate % Error Baud Rate (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% 115200 ...
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C8051F300/1/2/3/4/5 Table 14.6. Timer Settings for Standard Baud Rates Using an External 3.6864 MHZ Target Baud Rate % Error Baud Rate (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% ...
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Timers Each MCU includes 3 counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and one is a 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose use. These timers can ...
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C8051F300/1/2/3/4/5 The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to “12.1. Priority Crossbar Decoder” on page 104 ...
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Mode 1: 16-bit Counter/Timer Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun- ter/timers are enabled and configured in Mode 1 in the same manner as for Mode ...
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C8051F300/1/2/3/4/5 15.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The coun- ter/timer in TL0 is controlled using the Timer 0 control/status bits ...
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SFR Definition 15.1. R/W R/W R/W TF1 TR1 TF0 Bit7 Bit6 Bit5 Bit7: TF1: Timer 1 Overflow Flag. Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto- matically cleared when the CPU ...
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C8051F300/1/2/3/4/5 SFR Definition 15.2. R/W R/W R/W GATE1 C/T1 T1M1 Bit7 Bit6 Bit5 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled only when TR1 = ...
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SFR Definition 15.3. R/W R/W R/W — T2MH T2ML Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0b, Write = don’t care. Bit6: T2MH: Timer 2 High Byte Clock Select This bit selects the clock supplied to the Timer 2 high ...
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C8051F300/1/2/3/4/5 SFR Definition 15.4. R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0 SFR Definition 15.5. R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: ...
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Timer 2 Timer 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines the ...
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C8051F300/1/2/3/4/5 15.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 15.5. TMR2RLL holds the reload value for TMR2L; ...
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SFR Definition 15.8. TMR2CN: Timer 2 Control R/W R/W R/W TF2H TF2L TF2LEN Bit7 Bit6 Bit5 Bit7: TF2H: Timer 2 High Byte Overflow Flag Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00 ...
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C8051F300/1/2/3/4/5 SFR Definition 15.9. TMR2RLL: Timer 2 Reload Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: TMR2RLL: Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2. SFR Definition ...
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Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. Each capture/compare module has ...
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C8051F300/1/2/3/4/5 16.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of ...
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Capture/Compare Modules Each module can be configured to operate independently in one of six operation modes: Edge-triggered Capture, Software Timer, High Speed Output, Frequency Output, 8-bit Pulse Width Modulator, or 16-bit Pulse Width Modulator. Each module has Special Function ...
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C8051F300/1/2/3/4/5 16.2.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/ timer and copy it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). ...
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Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and ...
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C8051F300/1/2/3/4/5 16.2.3. High Speed Output Mode In High Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn) Setting the TOGn, MATn, ...
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Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out- put is toggled. The frequency of ...
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C8051F300/1/2/3/4/5 16.2.5. 8-Bit Pulse Width Modulator Mode Each module can be used independently to generate a pulse width modulated (PWM) output on its associ- ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA ...
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Pulse Width Modulator Mode A PCA module may also be operated in 16-bit PWM mode. In this mode, the 16-bit capture/compare mod- ule defines the number of PCA clocks for the low time of the PWM signal. When ...
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C8051F300/1/2/3/4/5 16.3. Watchdog Timer Mode A programmable watchdog timer (WDT) function is available through the PCA Module 2. The WDT is used to generate a reset if the time between writes to the WDT update register (PCA0CPH2) exceed a specified ...
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Note that the 8-bit offset held in PCA0CPH2 is compared to the upper byte of the 16-bit PCA counter. This offset value is the number of PCA0L overflows before a reset 256 PCA clocks may pass before the ...
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C8051F300/1/2/3/4/5 Table 16.3. Watchdog Timer Timeout Intervals System Clock (Hz) 24,500,000 24,500,000 24,500,000 18,432,000 18,432,000 18,432,000 11,059,200 11,059,200 11,059,200 3,062,500 3,062,500 3,062,500 32,000 32,000 32,000 Notes: 1. Assumes SYSCLK / 12 as the PCA clock source, and a PCA0L value ...
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Register Descriptions for PCA Following are detailed descriptions of the special function registers related to the operation of the PCA. SFR Definition 16.1. PCA0CN: PCA Control R/W R/W R — Bit7 Bit6 Bit5 Bit7: CF: PCA Counter/Timer ...
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C8051F300/1/2/3/4/5 SFR Definition 16.2. PCA0MD: PCA Mode R/W R/W R/W CIDL WDTE WDLCK Bit7 Bit6 Bit5 Bit7: CIDL: PCA Counter/Timer Idle Control. Specifies PCA behavior when CPU is in Idle Mode. 0: PCA continues to function normally while the system ...
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SFR Definition 16.3. PCA0CPMn: PCA Capture/Compare Mode R/W R/W R/W PWM16n ECOMn CAPPn CAPNn Bit7 Bit6 Bit5 PCA0CPMn Address: PCA0CPM0 = 0xDA ( PCA0CPM1 = 0xDB ( PCA0CPM2 = 0xDC ( Bit7: PWM16n: 16-bit ...
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C8051F300/1/2/3/4/5 SFR Definition 16.4. PCA0L: PCA Counter/Timer Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7–0: PCA0L: PCA Counter/Timer Low Byte. The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer. SFR Definition 16.5. PCA0H: PCA ...
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SFR Definition 16.6. PCA0CPLn: PCA Capture Module Low Byte R/W R/W R/W Bit7 Bit6 Bit5 PCA0CPLn Address: PCA0CPL0 = 0xFB ( PCA0CPL1 = 0xE9 ( PCA0CPL2 = 0xEB ( Bits7–0: PCA0CPLn: PCA Capture Module ...
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C8051F300/1/2/3/4 OTES 172 Rev. 2.9 ...
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C2 Interface C8051F300/1/2/3/4/5 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow Flash programming and in-system debugging with the production part installed in the end application. The C2 interface operates using only two pins: a bi-directional ...
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C8051F300/1/2/3/4/5 C2 Register Definition 17.3. REVID: C2 Revision ID Bit7 Bit6 Bit5 This read-only register returns the 8-bit revision ID: 0x00 (Revision A) C2 Register Definition 17.4. FPCTL: C2 Flash Programming Control Bit7 Bit6 Bit5 Bits7–0 FPCTL: Flash Programming Control ...
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C2 Pin Sharing The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and Flash programming functions may be performed. This is possible because C2 communication is typically performed when the device ...
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C8051F300/1/2/3/4 OCUMENT HANGE IST Revision 2.3 to Revision 2.4 • Removed preliminary tag. • Changed all references of MLP package to QFN package. • Pinout chapter: Figure 4.3: Changed title to “Typical QFN-11 Solder Paste Mask.” • ...
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N : OTES C8051F300/1/2/3/4/5 Rev. 2.9 177 ...
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