MA240017 Microchip Technology, MA240017 Datasheet - Page 38

• Manufacturer Part Number: MA240017
• Description: MODULE PLUG-IN PIC24F16KA102 PIM
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of MA240017

• Accessory Type: Plug-In Module (PIM) - PIC24F16KA102
• Product: Microcontroller Modules
• Data Bus Width: 16 bit
• Core Processor: PIC24F16KA102
• Operating Supply Voltage: 3 V to 3.6 V
• Development Tools By Supplier: Integrated Development Environment, Assembler, ANSI C Compiler
• Processor Series: PIC24F
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC24
• Silicon Core Number: PIC24F
• Silicon Family Name: PIC24FxxKAxx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Explorer 16 (DM240001 or DM240002)
• For Use With: DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 4-20:
TABLE 4-21:
TABLE 4-22:
TABLE 4-23:
RCON
OSCCON
CLKDIV
OSCTUN
REFOCON
HLVDCON
Legend:
Note
DSWSRC
DSGPR0
DSGPR1
Legend:
Note
NVMCON
NVMKEY
Legend:
Note
PMD1
PMD2
PMD3
PMD4
Legend:
File Name
File Name
DSCON
File Name
File Name
1:
2:
1:
1:
Addr
0760
0766
Addr
0758
075A
075C
075E
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values are dependent on type of Reset.
OSCCON register Reset values are dependent on configuration fuses and by type of Reset.
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The Deep Sleep registers are only reset on a V
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
0770
0772
0774
0776
Addr
074E
0740
0742
0744
0748
0756
Bit 15
CLOCK CONTROL REGISTER MAP
DEEP SLEEP REGISTER MAP
NVM REGISTER MAP
PMD REGISTER MAP
WR
Bit 15
DSEN
Bit 15
HLVDEN
—
TRAPR
ROEN
Bit 15
—
—
—
—
—
ROI
—
—
WREN
Bit 14
Bit 14
—
—
—
—
—
IOPUWR SBOREN
Bit 14
COSC2
DOZE2
Bit 14
—
—
—
—
—
WRERR
Bit 13
T3MD
Bit 13
—
—
—
—
Bit 13
ROSSLP
COSC1
HLSIDL
DOZE1
Bit 13
—
—
—
Bit 12 Bit 11
T2MD T1MD
PGMONLY
—
—
—
Bit 12
—
Bit 12
COSC0
DOZE0
ROSEL
—
—
Bit 12
—
—
—
—
—
—
DD
POR event.
Bit 11
CMPMD
—
—
Bit 11
Bit 10
RODIV3
DOZEN
—
—
—
—
—
Bit 11
—
—
—
—
Bit 10
—
—
RTCCMD
Bit 10
Bit 9
RCDIV2
RODIV2
NOSC2
—
—
DPSLP
—
—
—
Bit 10
—
—
Bit 9
—
—
IC1MD
Bit 9
RCDIV1
RODIV1 RODIV0
Bit 8
NOSC1
Deep Sleep General Purpose Register 0
Deep Sleep General Purpose Register 1
—
—
—
—
—
Bit 9
—
—
—
Bit 8
—
—
CRCPMD
DSINT0
I2C1MD
RCDIV0
PMSLP
NOSC0
Bit 8
Bit 7
Bit 8
—
—
—
—
—
NVMKEY7
Bit 7
—
CLKLOCK
DSFLT
Bit 7
EXTR
VDIR
U2MD
Bit 7
—
Bit 6
—
—
—
—
—
—
NVMKEY6
ERASE
Bit 6
Bit 6
BGVST
—
—
SWR
Bit 6
U1MD
Bit 5
—
—
—
—
—
—
—
NVMKEY5 NVMKEY4 NVMKEY3 NVMKEY2 NVMKEY1 NVMKEY0 0000
NVMOP5
Bit 5
SWDTEN
Bit 5
IRVST
LOCK
TUN5
—
—
Bit 5
—
—
EEMD
Bit 4
—
—
—
NVMOP4
DSWDT
Bit 4
Bit 4
—
WDTO
TUN4
Bit 4
REFOMD
—
—
—
—
SPI1MD
Bit 3
—
—
NVMOP3
DSRTCC DSMCLR
Bit 3
Bit 3
HLVDL3
—
SLEEP
TUN3
Bit 3
CF
—
—
CTMUMD
Bit 2
—
—
—
NVMOP2
Bit 2
Bit 2
HLVDL2
—
TUN2
Bit 2
IDLE
—
—
—
HLVDMD
Bit 1
DSBOR
—
—
—
NVMOP1
Bit 1
SOSCEN OSWEN (Note 2)
HLVDL1
—
Bit 1
TUN1
Bit 1
BOR
—
—
ADC1MD
OC1MD
RELEASE
Bit 0
DSPOR
NVMOP0
—
—
Bit 0
HLVDL0
TUN0
Bit 0
Bit 0
POR
—
—
All Resets
Resets
0000
0000
0000
0000
(Note 1)
Resets
0000
0000
0000
0000
Resets
0000
3140
0000
0000
0000
All
All
All
(1)
(1)