MA240017 Microchip Technology, MA240017 Datasheet - Page 27

• Manufacturer Part Number: MA240017
• Description: MODULE PLUG-IN PIC24F16KA102 PIM
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of MA240017

• Accessory Type: Plug-In Module (PIM) - PIC24F16KA102
• Product: Microcontroller Modules
• Data Bus Width: 16 bit
• Core Processor: PIC24F16KA102
• Operating Supply Voltage: 3 V to 3.6 V
• Development Tools By Supplier: Integrated Development Environment, Assembler, ANSI C Compiler
• Processor Series: PIC24F
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC24
• Silicon Core Number: PIC24F
• Silicon Family Name: PIC24FxxKAxx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Explorer 16 (DM240001 or DM240002)
• For Use With: DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.0
As with Harvard architecture devices, the PIC24F
microcontrollers feature separate program and data
memory space and busing. This architecture also
allows the direct access of program memory from the
data space during code execution.
4.1
The program address memory space of the PIC24F
devices is 4M instructions. The space is addressable by
a 24-bit value derived from either the 23-bit Program
Counter (PC) during program execution, or from a table
operation or data space remapping, as described in
Section 4.3 “Interfacing Program and Data Memory
Spaces”.
FIGURE 4-1:
© 2009 Microchip Technology Inc.
Note:
MEMORY ORGANIZATION
Program Address Space
Memory areas are not displayed to scale.
PROGRAM SPACE MEMORY MAP FOR PIC24F16KA102 FAMILY DEVICES
Device Config Registers
Alternate Vector Table
Interrupt Vector Table
(2816 instructions)
PIC24F08KA102
Program Memory
GOTO Instruction
Unimplemented
Data EEPROM
Reset Address
DEVID (2)
Reserved
Reserved
Reserved
Read ‘0’
Flash
Preliminary
PIC24F16KA102 FAMILY
The user access to the program memory space is
restricted to the lower half of the address range
(000000h to 7FFFFFh). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
Memory maps for the PIC24F16KA102 family of
devices are displayed in Figure 4-1.
Device Config Registers
Alternate Vector Table
Interrupt Vector Table
(5632 instructions)
PIC24F16KA102
Program Memory
GOTO Instruction
Unimplemented
Reset Address
Data EEPROM
User Flash
DEVID (2)
Reserved
Reserved
Reserved
Read ‘0’
000000h
000002h
000004h
0000FEh
000100h
000104h
0001FEh
000200h
0015FEh
002BFE
7FFE00h
7FFFFFh
800000h
F7FFFEh
F80000h
F80010h
F80012h
FEFFFEh
FF0000h
FFFFFFh
DS39927B-page 25