MA240017 Microchip Technology, MA240017 Datasheet - Page 144
MA240017
Manufacturer Part Number
MA240017
Description
MODULE PLUG-IN PIC24F16KA102 PIM
Manufacturer
Microchip Technology
Series
PIC®r
Specifications of MA240017
Accessory Type
Plug-In Module (PIM) - PIC24F16KA102
Product
Microcontroller Modules
Data Bus Width
16 bit
Core Processor
PIC24F16KA102
Operating Supply Voltage
3 V to 3.6 V
Development Tools By Supplier
Integrated Development Environment, Assembler, ANSI C Compiler
Processor Series
PIC24F
Silicon Manufacturer
Microchip
Core Architecture
PIC
Core Sub-architecture
PIC24
Silicon Core Number
PIC24F
Silicon Family Name
PIC24FxxKAxx
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
Explorer 16 (DM240001 or DM240002)
For Use With
DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MA240017
Manufacturer:
MICROCHIP
Quantity:
12 000
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PIC24F16KA102 FAMILY
REGISTER 17-3:
REGISTER 17-4:
DS39927B-page 142
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-10
bit 9-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-5
bit 4
bit 0
Note 1:
AMSK7
R/W-0
U-0
U-0
U-0
—
—
—
2:
3:
To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit needs to be set.
To enable the actual OC1 output, the OCPWM1 module has to be enabled.
Bits 3, 2 and 1 are described in related chapters.
Unimplemented: Read as ‘0’
SMBUSDEL: SMBus SDA Input Delay Select bit
1 = The I
0 = The 1
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘0’
AMSK<9:0>: Mask for Address Bit x Select bits
1 = Enable masking for bit x of incoming message address; bit match not required in this position
0 = Disable masking for bit x; bit match required in this position
U-0
U-0
AMSK6
—
—
R/W-0
U-0
—
I2C1MSK: I2C1 SLAVE MODE ADDRESS MASK REGISTER
PADCFG1: PAD CONFIGURATION CONTROL REGISTER
2
2
C module is configured for a longer SMBus input delay (nominal 300 ns delay)
C module is configured for a legacy input delay (nominal 150 ns delay)
W = Writable bit
‘1’ = Bit is set
U-0
U-0
W = Writable bit
‘1’ = Bit is set
—
—
AMSK5
R/W-0
U-0
—
SMBUSDEL
R/W-0
U-0
—
AMSK4
R/W-0
U-0
—
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
OC1TRIS
R/W-0
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
AMSK3
R/W-0
(3)
U-0
—
RTSECSEL1
R/W-0
U-0
—
AMSK2
R/W-0
U-0
—
(1,3)
x = Bit is unknown
© 2009 Microchip Technology Inc.
RTSECSEL0
x = Bit is unknown
AMSK9
AMSK1
R/W-0
R/W-0
R/W-0
U-0
—
(1,3)
AMSK8
AMSK0
R/W-0
R/W-0
U-0
U-0
—
—
bit 8
bit 0
bit 8
bit 0
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