IDT72T55248L5BB IDT, Integrated Device Technology Inc, IDT72T55248L5BB Datasheet - Page 23

• Manufacturer Part Number: IDT72T55248L5BB
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55248L5BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55248L5BB

WCLKS. Subsequent read operations will cause PAF to go HIGH at the
conditions described in Table 3. If further read operations occur, without write
operations, PAE will go LOW when there are n words in the Queue, where n
is the empty offset value. Continuing read operations will cause the Queue to
become empty. Then the last word has been read from the Queue, the EF will
go LOW inhibiting further read operations. REN is ignored when the Queue is
empty.
register-buffered outputs. IDT Standard mode is available when the device is
configured in both Single Data Rate and Double Data Rate mode. Relevant
timing diagrams for IDT Standard mode can be found in Figures 14, 15, 16.
FIRST WORD FALL THROUGH MODE (FWFT)
outlined in Table 4. To write data into to the Queue, WCS must be LOW. Data
presented to the DATA IN lines will be clocked into the Queue on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (OR)
flag will go LOWafter 3rd rising edge of RCLK. Subsequent writes will continue
to fill up the Queue. PAE will go HIGH after n + 2 words have been loaded into
the Queue, where n is the empty offset value. The default setting for these values
are listed in Table 4. This parameter is also user programmable as described
in the serial writing and reading of offset registers section.
will cause the Programmable Almost-Full flag (PAF) to go LOW. Again, if no
reads are performed, the PAF will go LOW after (8,193-m) writes for the
IDT72T55248, (16,385-m) writes for the IDT72T55258, and (32,769-m) writes
for the IDT72T55268. This is assuming the I/O bus width is configured to x40.
TABLE 3 — STATUS FLAGS FOR IDT STANDARD MODE
NOTE:
1. n, m = 7 if FSEL[1:0] = 00, n, m = 63 if FSEL[1:0] = 01, n, m = 127 if FSEL[1:0] = 10, n, m = 1023 if FSEL[1:0] = 11.
TABLE 4 — STATUS FLAGS FOR FWFT MODE
NOTE:
1. n, m = 7 if FSEL[1:0] = 00, n, m = 63 if FSEL[1:0] = 01, n, m = 127 if FSEL[1:0] = 10, n, m = 1023 if FSEL[1:0] = 11.
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
OW = x40
OW = x20
OW = x10
OW = x40
OW = x20
OW = x10
If the Queue is full, the first read operation will cause FF to go HIGH after two
When configured in IDT Standard mode, the EF and FF outputs are double
In this mode, the status flags OR, IR, PAE, and PAF operate in the manner
Continuing to write data into the Queue without performing read operations
Number of
Words in
Queue
Number of
Words in
Queue
(n+1) to (8,192 - m)
(n+2) to (8,193 - m)
IDT72T55248
IDT72T55248
1 to n
1 to n+1
8,192
8,193
0
0
(1)
(1)
(n+1) to (16,384 - m)
(n+2) to (16,385 - m)
IDT72T55258
IDT72T55248
IDT72T55258
IDT72T55248
1 to n
1 to n+1
16,384
16,385
0
0
(1)
(1)
(n+1) to (32,768 - m)
(n+2) to (32,769 - m)
IDT72T55268
IDT72T55258
IDT72T55248
IDT72T55268
IDT72T55258
IDT72T55248
1 to n
1 to n+1
32,768
32,769
0
0
(1)
23
(1)
If the I/O is x20, then PAF will go LOW after (16,385-m) writes for the
IDT72T55248, (32,769-m) writes for the IDT72T55258, and (65,537-m) writes
for the IDT72T55268. If the I/O is x10, then PAF will go LOW after (32,769-m)
writes for the IDT72T55248, (65,537-m) writes for the IDT72T55258, and
(131,073-m) writes for the IDT72T55268. The offset “m” is the full offset value.
The default setting for these values are listed in Table 4. This parameter is also
user programmable. See the section on serial writing and reading of offset
registers for details.
write operations. If no reads are performed after a reset, IR will go LOW after
D writes to the Queue. If the I/O bus width is configured to x40, then D = 8,193
writes for the IDT72T55248, 16,385 writes for the IDT72T55258, and 32,769
writes for the IDT72T55268. If the I/O is x20, then D = 16,385 writes for the
IDT72T55248, 32,769 writes for the IDT72T55258, and 65,537 writes for the
IDT72T55268. If the I/O is x10, then D = 32,769 writes for the IDT72T55248,
65,537 writes for the IDT72T55258, and 131,073 writes for the IDT72T55268.
WCLKs after RCLK. Subsequent read operations will cause PAF to go HIGH
at the conditions described in Table 4. If further read operations occur, without
write operations, PAE will go LOW when there are n words in the Queue, where
n is the empty offset value. Continuing read operations will cause the Queue to
become empty. Then the last word has been read from the Queue, the OR will
go HIGH inhibiting further read operations. RCS is ignored when the Queue
is empty.
and the IR flag output is double register-buffered. Relevant timing diagrams for
FWFT mode can be found in Figures 17, 18, 19.
When the Queue is full, the Input Ready (IR) will go LOW, inhibiting further
If the Queue is full, the first read operation will cause IR to go HIGH after two
When configured in FWFT mode, the OR flag output is triple register-buffered
(n+1) to (65,536 - m)
(n+2) to (65,537 - m)
IDT72T55268
IDT72T55268
IDT72T55258
IDT72T55258
1 to n
1 to n+1
65,536
65,537
0
0
(1)
(1)
(n+1) to (131,072 - m)
(n+2) to (131,073 - m)
IDT72T55268
IDT72T55268
COMMERCIAL AND INDUSTRIAL
1 to n
1 to n+1
131,072
131,073
0
0
(1)
(1)
TEMPERATURE RANGES
FEBRUARY 01, 2009
FF PAF PAE EF
FF PAF PAE EF
H
H
H
L
H
H
H
L
H
H
L
L
H
H
L
L
L
L
H
H
L
L
H
H
6157 drwSFT
L
H
H
H
L
H
H
H