IDT72T55248L5BB IDT, Integrated Device Technology Inc, IDT72T55248L5BB Datasheet - Page 21

• Manufacturer Part Number: IDT72T55248L5BB
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55248L5BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55248L5BB

reset will determine the value. Table 1 lists the four offset values and how to select
them. For programming the offset values to a specific number, use the serial
programming signals (SCLK, SWEN, SREN, FWFT/SI) to load the value into
the offset register. You may also use the JTAG port on this device to load the
offset value. Keep in mind that you must disable the serial programming signals
if you plan to use the JTAG port for loading the offset values. To disable the serial
programming signals, tie SCLK, SWEN, SREN, and SI to V
explanation of the serial and JTAG programming of the flag offset values is
provided in the next section.
or 1.5V HSTL / 1.8V eHSTL levels. The state of the IOSEL input will determine
which I/O level will be selected. If IOSEL is HIGH then the applicable I/Os will
be 1.5V HSTL or 1.8V eHSTL, depending on the voltage level applied to V
and V
= 0.9V. If IOSEL is LOW then the applicable I/Os will be 2.5V LVTTLV
0. As noted in the Pin Description section, IOSEL is a CMOS input and must be
tied to either V
OS[1:0] will be held constant and indicates which internal Queue the read and
write port will select for initial operation. Data will be written to or read from this
internal Queue on the first valid write and read operation after master reset.
SERIAL WRITING AND READING OF OFFSET REGISTERS
programmed with another value. One of four default values are detected based
on the state of the FSEL[1:0] inputs, discussed in the Functional Description
NOTES:
* Programming done using the JTAG port.
1. The programming methods apply to both IDT Standard mode and FWFT mode.
2. Parallel programming is not featured in this device.
3. The number of bits includes programming to all four dedicated PAE/PAF offset registers.
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
Don’t
care
except
0008 &
0007
0008
0007
TDI*
I/O Level Selection. The I/Os can be selected for either 2.5V LVTTL levels
Input and Output Selection. During master reset, the value of IS[1:0] and
These offset registers can be loaded with a default value or they can be user
REF
. For HSTL, V
TCK*
X
CC
or GND for proper operation.
SWEN
0
1
1
DDQ
and V
SREN
1
0
1
REF
= 0.75V and for eHSTL V
SCLK
X
Figure 3. Programmable Flag Offset Programming Methods
Serial write into register:
104 bits for the IDT72T55248
112 bits for the IDT72T55258
120 bits for the IDT72T55268
1 bit for each rising SCLK edge
starting with empty offset (LSB)
ending with full offset (MSB)
No Operation
Serial read from registers:
104 bits for the IDT72T55248
112 bits for the IDT72T55258
120 bits for the IDT72T55268
1 bit for each rising SCLK edge
starting with empty offset (LSB)
ending with full offset (MSB)
IW/OW = x40
CC
DDQ
. A thorough
and V
REF
DDQ
REF
=
21
section earlier. User programming of the offset values can be performed by
either the dedicated serial programming port or the JTAG port. The dedicated
serial port can be used to load or read the contents of the offset registers. The
offset registers are programmed and read sequentially and behave similar to
a shift register.
FWFT/SI, SWEN, SREN, and SDO pins. The total number of bits per device
is listed in Figure 4, Programmable Flag Offset Programming Methods. These
bits account for all four PAE/PAF offset registers in the device. To write to the
offset registers, set the serial write enable signal active (LOW), and on each rising
edge of SCLK one bit from the FWFT/SI pin is serially shifted into the flag offset
register chain. Once the complete number of bits has been programmed into all
four registers, the programming sequence is complete. To read values from the
offsets registers, set the serial read enable active (LOW). Then on each rising
edge of SCLK, one bit is shifted out to the serial data output. The serial read
enable must be kept LOW throughout the entire read operation. To stop reading
the offset register, disable the serial read enable (HIGH). There is serial read
enable to SCLK time for reading the offset registers, as the offset register data
for each Queue is temporarily stored in a scan chain. When data has been
completely read out of the offset registers, any additional read operations to the
offset register will result in zeros as the output data.
the JTAG port. To write to the offset registers using JTAG, set the instructional
register to the offset write command (Hex Value = 0x0008). The JTAG port will
load data into each of the offset registers in a similar fashion as the serial
programming described above. To read the values from the offset registers, set
The serial read and write operations are performed by the dedicated SCLK,
Reading and writing of the offset registers can also be accomplished using
Serial write into register:
112 bits for the IDT72T55248
120 bits for the IDT72T55258
128 bits for the IDT72T55268
1 bit for each rising SCLK edge
starting with empty offset (LSB)
ending with full offset (MSB)
Serial read from registers:
112 bits for the IDT72T55248
120 bits for the IDT72T55258
128 bits for the IDT72T55268
1 bit for each rising SCLK edge
starting with empty offset (LSB)
ending with full offset (MSB)
No Operation
IDT72T55258
IDT72T55268
IDT72T55278
IW/OW = x20
COMMERCIAL AND INDUSTRIAL
Serial write into register:
120 bits for the IDT72T55248
128 bits for the IDT72T55258
136 bits for the IDT72T55268
1 bit for each rising SCLK edge
starting with empty offset (LSB)
ending with full offset (MSB)
Serial read from registers:
120 bits for the IDT72T55248
128 bits for the IDT72T55258
136 bits for the IDT72T55268
1 bit for each rising SCLK edge
starting with empty offset (LSB)
ending with full offset (MSB)
No Operation
TEMPERATURE RANGES
IW/OW = x10
FEBRUARY 01, 2009
6157 drwAA