IDT72T55248L5BB IDT, Integrated Device Technology Inc, IDT72T55248L5BB Datasheet - Page 17

• Manufacturer Part Number: IDT72T55248L5BB
• Description: IC CTRL QUADMUX FLOW 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T55248L5BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T55248L5BB

AC ELECTRICAL CHARACTERISTICS
(Commercial: V
NOTES:
1. With exception to clock cycle frequency, these parameters apply to both DDR and SDR modes of operation.
2. Values guaranteed by design, not currently tested.
3. Industrial temperature range product for the 6-7ns speed grade is available as a standard device. All other speed grades available by special order.
IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with
Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4
Symbol
f
f
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
A
ASO
OE
PAES
PAEA
S1
S2
CLK1
CLK2
CLKH1
CLKH2
CLKL1
CLKL2
DS
DH
ENS
ENH
C
SCLK
SCKH
SCKL
SDS
SDH
SENS
SENH
RS
RSS
RSR
RSF
OLZ
OHZ
WFF
REF
CEF
CFF
PAFS
PAFA
ERCLK
CLKEN
D
RCSLZ
RCSHZ
SKEW1
SKEW2
SKEW3
(OE - Qn)
CC
Clock Cycle Frequency (WCLK & RCLK) SDR
Clock Cycle Frequency (WCLK & RCLK) DDR
Data Access Time
Clock Cycle Time SDR
Clock Cycle Time DDR
Clock High Time SDR
Clock High Time DDR
Clock Low Time SDR
Clock Low Time DDR
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Clock Cycle Frequency (SCLK)
Serial Output Data Access Time
Serial Clock Cycle
Serial Clock High
Serial Clock Low
Serial Data In Setup
Serial Data In Hold
Serial Enable Setup
Serial Enable Hold
Reset Pulse Width
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Impedance
Output Enable to Output in High-Impedance
Output Enable to Data Output Valid
Write Clock to FF or IR
Read Clock to EF or OR
Read Clock to Composite EF or OR
Write Clock to Composite FF or IR
Write Clock to Synchronous Programmable Almost-Full Flag
Read Clock to Synchronous Programmable Almost-Empty Flag
Write Clock to Asynchronous Programmable Almost-Full Flag
Read Clock to Asynchronous Programmable Almost-Empty Flag
RCLK to Echo RCLK Output
RCLK to Echo REN Output
Time Between Data Switching and ERCLK edge
RCLK to Active from High-Impedance
RCLK to High-Impedance
SKEW time between RCLK and WCLK for EF/OR and FF/IR
SKEW time between RCLK and WCLK for EF/OR and FF/IR in DDR mode
SKEW time between RCLK and WCLK for PAE and PAF
= 2.5V ± 0.15V, T
A
= 0°C to +70°C;Industrial: V
Parameter
CC
= 2.5V ± 0.15V, T
(1)
17
A
Min.
= -40°C to +85°C; JEDEC JESD8-A compliant)
IDT72T55248L5
IDT72T55258L5
IDT72T55268L5
100
200
0.6
2.3
4.5
2.3
4.5
1.5
0.5
1.5
0.5
0.6
0.6
0.6
0.4
10
45
45
15
15
10
Commercial
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
5
5
5
4
5
5
Max.
200
100
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
4.0
3.6
3.6
3.6
10
20
12
10
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Commercial & Industrial
COMMERCIAL AND INDUSTRIAL
Min.
IDT72T55248L6-7
IDT72T55258L6-7
IDT72T55268L6-7
100
200
0.6
6.7
2.8
6.0
2.8
6.0
2.0
0.5
2.0
0.5
0.8
0.8
0.8
0.5
13
45
45
15
15
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
5
5
5
7
7
TEMPERATURE RANGES
Max.
FEBRUARY 01, 2009
150
3.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8
3.8
4.3
3.8
3.8
3.8
75
—
—
—
—
—
—
—
—
—
—
10
20
—
—
—
—
—
—
—
—
—
—
15
12
12
—
—
—
—
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns