MT47H64M8CB-3:B Micron Technology Inc, MT47H64M8CB-3:B Datasheet - Page 72

IC DDR2 SDRAM 512MBIT 3NS 60FBGA

MT47H64M8CB-3:B

Manufacturer Part Number
MT47H64M8CB-3:B
Description
IC DDR2 SDRAM 512MBIT 3NS 60FBGA
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT47H64M8CB-3:B

Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
512M (64M x 8)
Speed
3ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
60-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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RESET Function
(CKE LOW Anytime)
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
DDR2 SDRAM applications may go into a reset state anytime during normal operation.
If an application enters a reset condition, CKE is used to ensure the DDR2 SDRAM
device resumes normal operation after re-initializing. All data will be lost during a reset
condition; however, the DDR2 SDRAM device will continue to operate properly if the
following conditions outlined in this section are satisfied.
The reset condition defined here assumes all supply voltages (V
V
operation. All other input pins of the DDR2 SDRAM device are a “Don’t Care” during
RESET with the exception of CKE.
WRITE burst), the memory controller must satisfy the timing parameter
turning off the clocks. Stable clocks must exist at the CK, CK# inputs of the DRAM before
CKE is raised HIGH, at which time the normal initialization sequence must occur. See
“Initialization” on page 16. The DDR2 SDRAM device is now ready for normal operation
after the initialization sequence. Figure 55 on page 73 shows the proper sequence for a
RESET operation.
If CKE asynchronously drops LOW during any valid operation (including a READ or
REF
) are stable and meet all DC specifications prior to, during, and after the RESET
72
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16 DDR2 SDRAM
©2004 Micron Technology, Inc. All rights reserved.
DD
, V
RESET Function
DD
Q, V
t
DELAY before
DD
L, and

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