MT47H64M8CB-3:B Micron Technology Inc, MT47H64M8CB-3:B Datasheet - Page 113

• Manufacturer Part Number: MT47H64M8CB-3:B
• Description: IC DDR2 SDRAM 512MBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H64M8CB-3:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
Table 45:
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
Parameter/Condition
Operating one bank active-precharge current:
t
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are
switching
Operating one bank active-read-precharge
current: I
=
t
valid commands; Address bus inputs are switching;
Data pattern is same as I
Precharge power-down current: All banks idle;
t
address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current: All banks idle;
t
control and address bus inputs are stable; Data bus
inputs are floating
Precharge standby current: All banks idle;
t
address bus inputs are switching; Data bus inputs are
switching
Active power-down current: All banks open;
t
inputs are stable; Data bus inputs are floating
Active standby current: All banks open;
(I
HIGH, CS# is HIGH between valid commands; Other
control and address bus inputs are switching; Data
bus inputs are switching
Operating burst write current: All banks open,
continuous burst writes; BL = 4, CL = CL (I
t
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are
switching
Operating burst read current: All banks open,
continuous burst reads, I
(I
t
valid commands; Address bus inputs are switching;
Data bus inputs are switching
Burst refresh current:
command at every
CS# is HIGH between valid commands; Other control
and address bus inputs are switching; Data bus inputs
are switching
DD
CK =
RCD =
CK =
CK =
CK (I
CK (I
CK =
RP =
DD
DD
t
CK (I
),
), AL = 0;
DD
DD
t
t
t
t
Specifications and Conditions
t
t
RAS =
RP (I
CK (I
CK (I
CK (I
CK (I
DD
t
); CKE is HIGH, CS# is HIGH; Other control and
); CKE is LOW; Other control and address bus
RCD (I
),
OUT
DD
DD
DD
DD
DD
t
RC =
t
t
); CKE is HIGH, CS# is HIGH between
RAS MAX (I
),
),
); CKE is LOW; Other control and
); CKE is HIGH, CS# is HIGH; Other
CK =
DDR2 I
Notes: 1–7; notes appear on page 114
= 0mA; BL = 4, CL = CL (I
DD
t
t
RAS =
RC =
); CKE is HIGH, CS# is HIGH between
t
RC (Idd),
t
t
CK (I
RFC (I
t
RC (I
DD
t
RAS MAX (I
DD
DD
t
OUT
DD
CK =
DD
Specifications and Conditions
DD
),
4W
t
),
RAS =
) interval; CKE is HIGH,
= 0mA; BL = 4, CL = CL
t
),
t
RAS =
RP =
t
t
CK (I
RAS =
t
DD
RAS MIN (I
t
RP (I
DD
t
RAS MAX (I
),
DD
t
); refresh
RAS MIN (I
t
RP =
DD
), AL = 0;
DD
); CKE is
t
CK =
), AL = 0;
t
RP (I
t
DD
CK =
t
),
DD
CK =
t
DD
DD
t
CK
CK
),
);
);
I
I
I
I
I
I
I
Sym
DD
DD
DD
DD
I
I
DD
DD
DD
I
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
0
1
5
113
Slow PDN exit
Fast PDN exit
MR[12] = 0
MR[12] = 1
x4, x8, x16
Config
x4, x8
x4, x8
x4, x8
x4, x8
x4, x8
x4, x8
x4, x8
x4, x8
x16
x16
x16
x16
x16
x16
x16
x16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
I
DD
512Mb: x4, x8, x16 DDR2 SDRAM
-25E
100
135
115
165
195
295
205
275
230
230
50
65
55
70
40
12
70
75
7
Specifications and Conditions
100
135
115
165
195
295
205
275
230
230
-25
50
65
55
70
40
12
70
75
7
120
105
150
170
250
180
235
180
185
-3E
90
45
55
50
60
35
12
65
70
7
©2004 Micron Technology, Inc. All rights reserved.
120
105
150
170
250
180
235
180
185
90
45
55
50
60
35
12
65
70
-3
7
-37E
110
135
140
205
145
195
170
175
80
95
40
45
45
50
30
12
55
60
7
110
130
160
155
170
-5E Units
115
115
165
80
90
35
40
40
45
25
12
45
50
7
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA