MT47H64M8CB-3:B Micron Technology Inc, MT47H64M8CB-3:B Datasheet - Page 48

IC DDR2 SDRAM 512MBIT 3NS 60FBGA

MT47H64M8CB-3:B

Manufacturer Part Number
MT47H64M8CB-3:B
Description
IC DDR2 SDRAM 512MBIT 3NS 60FBGA
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT47H64M8CB-3:B

Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
512M (64M x 8)
Speed
3ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
60-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Figure 29:
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
LDQS#/LDQS / UDQ#/UDQS 2
All DQs collectively 3
DQ (Last data valid)
DQ (First data valid)
DQS#/DQS, or
Data Output Timing –
Notes:
CK#
CK
T0 7
1.
2. DQ transitioning after DQS transitions define
3. All DQ must transition by
4.
5.
6.
7. READ command with CL = 3, AL = 0 issued at T0.
8. I/O balls, when entering or exiting HIGH-Z, are not referenced to a specific voltage level,
t
skew.
t
t
t
but to when the device begins to drive or no longer drives, respectively.
DQSCK is the DQS output window relative to CK and is the “long-term” component of DQS
AC is the DQ output window relative to CK and is the “long term” component of DQ skew.
LZ (MIN) and
HZ (MAX) and
T1
t
AC and
t LZ (MIN)
t
AC (MIN) are the first valid signal transitions.
t
AC (MAX) are the latest valid signal transitions.
T2
t
DQSCK
t LZ (MIN)
t RPRE
t
DQSQ after DQS transitions, regardless of
48
T3
t DQSCK 1 (MIN)
T3
T3
T3
T3n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3n
T3n
T3n
t AC 4 (MIN)
T4
512Mb: x4, x8, x16 DDR2 SDRAM
t
DQSQ window.
T4
T4
T4
T4n
T4n
T4n
T4n
t AC 4 (MAX)
T5
T5
T5
T5
©2004 Micron Technology, Inc. All rights reserved.
T5n
t DQSCK 1 (MAX)
T5n
T5n
T5n
t
AC.
T6
T6
T6
T6
t HZ (MAX)
t HZ (MAX)
T6n
t RPST
T6n
T6n
T6n
READs
T7

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