MT47H64M8CB-3:B Micron Technology Inc, MT47H64M8CB-3:B Datasheet - Page 53

• Manufacturer Part Number: MT47H64M8CB-3:B
• Description: IC DDR2 SDRAM 512MBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H64M8CB-3:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 34:
Figure 35:
COMMAND
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
DQS, DQS#
ADDRESS
CK#
A10
DQ
CK
VALID
WRITE 1
T0
a
Random WRITE Cycles
WRITE Interrupted by WRITE
2
2 clock requirement
Notes:
Notes:
NOP
T1
5
WL = 3
t
1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following
3. Three subsequent elements of data-in are applied in the programmed order following
4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. Each WRITE command may be to any bank.
6. Subsequent rising DQS signals must align to the clock within
1. BL = 8 required and auto precharge must be disabled (A10 = LOW).
2. WRITE command can be issued to any valid bank and row address (WRITE command at T0
3. Interrupting WRITE command must be issued exactly 2 x
4. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the inter-
5. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command cannot be issued to
6. Earliest WRITE-to-PRECHARGE timing for WRITE at T0 is WL + BL/2 +
7. Example shown uses AL = 0; CL = 4, BL = 8.
8. Subsequent rising DQS signals must align to the clock within
DQSS (NOM)
COMMAND
DQS, DQS#
ADDRESS
DI b.
DI n.
and T2 can be either same bank or different bank).
rupting WRITE command.
banks used for WRITEs at T0 and T2.
with T7 and not T5 (since BL = 8 from MR and not the truncated length).
VALID
VALID
WRITE 3
T2
CK#
DM
DQ
b
CK
4
2
WRITE
Bank,
Col b
T0
NOP
T3
D
a
IN
5
WL = 3
a + 1
D
WL ±
IN
t
WL = 2
CCD
NOP
T1
NOP
t
DQSS
a + 2
T4
D
8
IN
5
53
T1n
a + 3
D
IN
WRITE
Bank,
Col n
T2
DI
b
NOP
T5
D
b
IN
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
5
T2n
b + 1
D
IN
WL = 2
512Mb: x4, x8, x16 DDR2 SDRAM
NOP
6
T3
NOP
b + 2
DON’T CARE
T6
D
IN
8
5
T3n
b + 3
D
IN
t
CK from previous WRITE.
NOP
6
T4
DI
VALID
n
TRANSITIONING DATA
b + 4
T7
D
IN
t
8
t
DQSS.
DQSS.
6
TRANSITIONING DATA
T4n
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b + 5
D
IN
t
WR where
NOP
VALID
6
T5
b + 6
T8
D
IN
8
6
T5n
b + 7
D
IN
t
WR starts
VALID
DON’T CARE
WRITEs
NOP
T6
T9
6