MT46H8M16LFCF-10 Micron Technology Inc, MT46H8M16LFCF-10 Datasheet - Page 55

• Manufacturer Part Number: MT46H8M16LFCF-10
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H8M16LFCF-10

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 60-VFBGA
• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 15b
• Access Time (max): 7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 90mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timing Diagrams
Figure 31:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
DQ8 - DQ15 and UDQS, collectively
DQ0 - DQ7 and LDQS, collectively
DQ (First data no longer valid)
DQ (First data no longer valid)
DQ (First data no longer valid)
DQ (First data no longer valid)
x16 Data Output Timing –
Notes:
DQ (Last data valid)
DQ (Last data valid)
DQ (Last data valid)
DQ (Last data valid)
1. DQ transitioning after DQS transition define
2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
3.
4.
5.
6. The data valid window is derived for each DQS transition and is
7. DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, or DQ15.
UDQS
LDQS
and UDQS defines the upper byte.
t
DQS transition and ends with the last valid DQ transition.
t
t
DQSQ is derived at each DQS clock edge and is not cumulative over time and begins with
QH is derived from
HP is the lesser of
CK#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CK
1
1
2
2
2
2
2
2
2
7
7
7
7
7
7
7
2
7
2
2
7
7
6
6
T1
t HP
5
t
DQSQ,
t
CL or
t
HP:
t HP
5
t DQSQ
t QH
t
t
t
QH =
QH, and Data Valid Window
CH clock transition collectively when a bank is active.
t DQSQ
T2
4
t QH
Data Valid
3
55
window
Data Valid
4
T2
T2
T2
window
t HP
3
t
HP -
T2
T2
T2
5
t DQSQ
T2n
128Mb: 8 Meg x 16 Mobile DDR SDRAM
t QH
t
QHS.
t DQSQ
Data Valid
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t QH
4
window
3
t HP
T2n
Data Valid
T2n
T2n
4
window
3
5
T2n
T2n
T2n
t
T3
DQSQ window. LDQS defines the lower byte
t DQSQ
t QH
t DQSQ
t QH
4
t HP
Data Valid
3
window
Data Valid
5
4
window
T3
T3
T3
3
T3
T3n
T3
T3
t DQSQ
t DQSQ
t HP
t QH
t QH
Data Valid
5
4
4
Data Valid
window
©2004 Micron Technology, Inc. All rights reserved.
3
3
t
window
T3n
T3n
QH minus
T4
T3n
T3n
T3n
T3n
Timing Diagrams
t
DQSQ.