MT46H8M16LFCF-10 Micron Technology Inc, MT46H8M16LFCF-10 Datasheet - Page 28

IC DDR SDRAM 128MBIT 60VFBGA

MT46H8M16LFCF-10

Manufacturer Part Number
MT46H8M16LFCF-10
Description
IC DDR SDRAM 128MBIT 60VFBGA
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheets

Specifications of MT46H8M16LFCF-10

Format - Memory
RAM
Memory Type
Mobile DDR SDRAM
Memory Size
128M (8Mx16)
Speed
100MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Package / Case
60-VFBGA
Organization
8Mx16
Density
128Mb
Address Bus
15b
Access Time (max)
7ns
Maximum Clock Rate
104MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
90mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT46H8M16LFCF-10
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT46H8M16LFCF-10 IT
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT46H8M16LFCF-10 IT TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT46H8M16LFCF-10 TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 16:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
READ-to-PRECHARGE
Notes:
COMMAND
COMMAND
1. D
2. BL = 4 or an interrupted burst of 8.
3. Shown with nominal
4. READ-to-PRECHARGE equals 2 clocks, which allows 2 data pairs of data-out.
5. A READ command with auto precharge enabled, provided
6. PRE = PRECHARGE command; ACT = ACTIVE command.
ADDRESS
ADDRESS
precharge to be performed at x number of clock cycles after the READ command, where x =
BL / 2.
OUT
DQS
DQS
CK#
CK#
DQ
DQ
CK
CK
5
5
n = data-out from column n.
Bank a,
Bank a,
READ
Col n
READ
Col n
T0
T0
t
CL = 2
AC,
NOP
NOP
T1
t
T1
DQSCK, and
CL = 3
28
T1n
T1n
128Mb: 8 Meg x 16 Mobile DDR SDRAM
(a or all)
(a or all)
D
Bank a,
Bank a,
OUT
n
T2
T2
PRE
PRE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DQSQ.
D
n + 1
T2n
T2n
OUT
D
OUT
n
D
T3
NOP
T3
NOP
n + 2
OUT
DON’T CARE
t
t
RP
RP
D
n + 1
T3n
OUT
T3n
D
n + 3
t
OUT
RAS (MIN) is met, would cause a
D
n + 2
©2004 Micron Technology, Inc. All rights reserved.
T4
NOP
T4
OUT
NOP
TRANSITIONING DATA
D
n + 3
OUT
Bank a,
Operations
Bank a,
T5
T5
Row
ACT
Row
ACT

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