MT46H8M16LFCF-10 Micron Technology Inc, MT46H8M16LFCF-10 Datasheet - Page 5

• Manufacturer Part Number: MT46H8M16LFCF-10
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H8M16LFCF-10

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 60-VFBGA
• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 15b
• Access Time (max): 7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 90mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3:
FBGA Part Marking Decoder
General Description
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
128Mb Mobile DDR SDRAM Part Numbers
Due to space limitations, FBGA-packaged components have an abbreviated part
marking that is different from the part number. Micron’s new FBGA Part Marking
Decoder makes it easier to understand this part marking. Visit the Web site at
www.micron.com/decoder.
The 128Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access
memory containing 134,271,728 bits. It is internally configured as a quad-bank DRAM.
Each of the 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits.
The 128Mb Mobile DDR SDRAM uses a double data rate architecture to achieve high-
speed operation. The double data rate architecture is essentially a 2n-prefetch architec-
ture with an interface designed to transfer two data words per clock cycle at the I/O
balls. A single read or write access for the 128Mb DDR SDRAM effectively consists of a
single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O balls.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the Mobile DDR SDRAM
during READs and by the memory controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for WRITEs. The x16 offering has two data
strobes, one for the lower byte and one for the upper byte.
The 128Mb Mobile DDR SDRAM operates from a differential clock (CK and CK#); the
crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of
CK. Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the Mobile DDR SDRAM are burst oriented; accesses start at
a selected location and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The address bits registered coin-
cident with the ACTIVE command are used to select the bank and row to be accessed.
The address bits registered coincident with the READ or WRITE command are used to
select the bank and the starting column location for the burst access.
The Mobile DDR SDRAM provides for programmable READ or WRITE burst lengths of 2,
4, or 8. An auto precharge function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
As with standard SDR SDRAMs, the pipelined, multibank architecture of Mobile DDR
SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by
hiding row precharge and activation time.
MT46H8M16LFCF-75
MT46H8M16LFCF-75IT
MT46H8M16LFCF-10
MT46H8M16LFCF-10IT
Part Number
Configuration
8 Meg x 16
8 Meg x 16
8 Meg x 16
8 Meg x 16
5
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Programmable drive
Programmable drive
Programmable drive
Programmable drive
I/O Drive Level
FBGA Part Marking Decoder
©2004 Micron Technology, Inc. All rights reserved.
Temperature Option
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C