MT41J64M16LA-187E:B TR Micron Technology Inc, MT41J64M16LA-187E:B TR Datasheet - Page 98

• Manufacturer Part Number: MT41J64M16LA-187E:B TR
• Description: IC DDR3 SDRAM 1GBIT 96FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J64M16LA-187E:B TR

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 533MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 96-FBGA
• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 265mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1378-2

Figure 45: DLL Disable Mode to DLL Enable Mode
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. F 11/08 EN
Command
ODT 10
CK#
CKE
CK
ODTL off + 1 × t CK
7
NOP
T0
Notes:
SRE 1
Ta0
10. Static LOW in case R
1. Enter SELF REFRESH.
2. Exit SELF REFRESH.
3. Wait
4. Wait
5. Wait
6. Wait
7. Starting with the idle state.
8. Change frequency.
9. Clock must be stable at least
The clock frequency range for the DLL disable mode is specified by the parameter
t
supported.
DLL disable mode will affect the read data clock to data strobe relationship (
but not the data strobe to data relationship (
line up read data to the controller time domain.
Compared to the DLL on mode where
cycles after the READ command, the DLL disable mode
after the READ command (see Figure 46 on page 99).
WRITE operations function similarly between the DLL enable and DLL disable modes;
however, ODT functionality is not allowed with DLL disable mode.
CK
DLL
t CKSRE
NOP
Ta1
_
t
t
t
t
DIS
XS, then set MR1[0] to “0” to enable DLL.
MRD, then set MR0[8] to “1” to begin DLL RESET.
MRD, update registers (CL, CWL, and write recovery may be necessary).
MOD, any valid command.
. Due to latency counter and timing restrictions, only CL = 6 and CWL = 6 are
Tb0
t CKESR
8
TT
_
NOM
Tc0
or R
98
t
CKSRX.
t CKSRX 9
TT
Tc1
_
WR
t
is enabled; otherwise, static LOW or HIGH.
DQSCK starts from the rising clock edge AL + CL
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SRX 2
Td0
t
DQSQ,
t XS
1Gb: x4, x8, x16 DDR3 SDRAM
MRS 3
Te0
t
QH). Special attention is needed to
t
t MRD
DQSCK starts AL + CL - 1 cycles
Indicates A Break in
Time Scale
MRS 4
Tf0
©2006 Micron Technology, Inc. All rights reserved.
t MRD
t DLLK
MRS 5
Tg0
Commands
t
Don’t Care
DQSCK)
Valid 6
Valid
Th0