MT41J64M16LA-187E:B TR Micron Technology Inc, MT41J64M16LA-187E:B TR Datasheet - Page 91

• Manufacturer Part Number: MT41J64M16LA-187E:B TR
• Description: IC DDR3 SDRAM 1GBIT 96FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J64M16LA-187E:B TR

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 533MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 96-FBGA
• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 265mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1378-2

Commands
Truth Tables
Table 62:
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. F 11/08 EN
Function
MODE REGISTER SET
REFRESH
Self refresh entry
Self refresh exit
Single-bank PRECHARGE
PRECHARGE all banks
Bank ACTIVATE
WRITE
WRITE with
auto
precharge
READ
READ with
auto
precharge
NO OPERATION
Device DESELECTED
Power-down entry
Power-down exit
ZQ CALIBRATION LONG
ZQ CALIBRATION SHORT
BL8MRS,
BC4MRS
BC4OTF
BL8OTF
BL8MRS,
BC4MRS
BC4OTF
BL8OTF
BL8MRS,
BC4MRS
BC4OTF
BL8OTF
BL8MRS,
BC4MRS
BC4OTF
BL8OTF
Truth Table – Command
Notes 1–5 apply to the entire table
Notes:
Symbol
WRAPS4
WRAPS8
RDAPS4
RDAPS8
WRAP
WRS4
WRS8
RDAP
PREA
ZQCL
ZQCS
RDS4
RDS8
1. Commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the
2. RESET# is LOW enabled and used only for asynchronous reset. Thus, RESET# must be held
3. The state of ODT does not affect the states described in this table.
MRS
NOP
ACT
PDX
DES
PDE
REF
SRE
SRX
PRE
WR
RD
clock. The MSB of BA, RA, and CA are device-density and configuration-dependent.
HIGH during any normal operation.
Cycle
Prev
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
CKE
Cycle
Next
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
CS# RAS# CAS# WE#
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
V
X
V
V
L
L
L
L
L
L
91
H
H
H
H
H
H
H
H
H
V
X
V
V
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
H
H
H
H
H
H
H
H
H
V
X
V
V
L
L
L
L
L
L
L
L
L
L
L
[2:0]
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
V
V
V
V
X
V
V
V
X
X
1Gb: x4, x8, x16 DDR3 SDRAM
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
An
V
V
V
V
V
V
X
V
V
X
X
Row address (RA)
A12
V
V
V
V
V
V
H
V
H
V
H
V
H
V
X
V
V
X
X
OP code
©2006 Micron Technology, Inc. All rights reserved.
L
L
L
L
A10
H
H
H
H
V
V
V
H
H
H
H
V
X
V
V
L
L
L
L
L
L
L
L
Commands
A[11,
9:0]
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
V
V
V
V
V
V
X
V
V
X
X
Notes
6, 11
6, 7
10
12
6
8
8
8
8
8
8
8
8
8
8
8
8
9
6