M58LT256JST8ZA6E NUMONYX, M58LT256JST8ZA6E Datasheet - Page 28

• Manufacturer Part Number: M58LT256JST8ZA6E
• Description: IC FLASH 256MBIT 85NS 64TBGA
• Manufacturer: NUMONYX

Specifications of M58LT256JST8ZA6E

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 256M (16Mx16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Command interface
4.12
4.13
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Program/Erase Resume command
The Program/Erase Resume command restarts the program or erase operation suspended
by the Program/Erase Suspend command. One bus write cycle is required to issue the
command, and the command can be issued to any address.
The Program/Erase Resume command does not change the read mode of the banks. If the
suspended bank was in read Status Register, read electronic signature or read CFI query
mode, the bank remains in that mode and outputs the corresponding data.
If a program command is issued during a block erase suspend, then the erase cannot be
resumed until the program operation completes.
See
Figure 24: Erase suspend and resume flowchart and pseudocode
the Program/Erase Resume command.
Protection Register Program command
The Protection Register Program command programs the user OTP segments of the
Protection Register and the two Protection Register Locks.
The device features 16 OTP segments of 128 bits and one OTP segment of 64 bits, as
shown in
The segments are programmed one word at a time. When shipped all bits in the segment
are set to ‘1’. The user can only program the bits to ‘0’.
Two bus write cycles are required to issue the Protection Register Program command.
●
●
Read operations to the bank being programmed output the Status Register content after the
program operation has started. Attempting to program a previously protected Protection
Register results in a Status Register error.
The Protection Register program cannot be suspended. Dual operations between the
parameter bank and the Protection Register memory space are not allowed (see
Dual operation limitations
The two Protection Register Locks protect the OTP segments from further modification. The
protection of the OTP segments is not reversible. Refer to
memory map
See
flowchart for using the Protection Register Program command.
Appendix
Appendix
The first bus cycle sets up the Protection Register Program command.
The second latches the address and data to be programmed to the Protection Register
and starts the Program/Erase Controller.
Figure 4: Protection Register memory
and
C,
C,
Figure 22: Program suspend and resume flowchart and
Figure 26: Protection Register program flowchart and pseudocode
Table 8: Protection Register locks
for details)
map.
for details on the lock bits.
Figure 4: Protection Register
M58LT256JST, M58LT256JSB
for flowcharts for using
pseudocode, and
Table 15:
for a