M58LT256JST8ZA6E NUMONYX, M58LT256JST8ZA6E Datasheet - Page 13

• Manufacturer Part Number: M58LT256JST8ZA6E
• Description: IC FLASH 256MBIT 85NS 64TBGA
• Manufacturer: NUMONYX

Specifications of M58LT256JST8ZA6E

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 256M (16Mx16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M58LT256JST, M58LT256JSB
2
2.1
2.2
2.3
2.4
2.5
2.6
Signal descriptions
See
connected to this device.
Address inputs (A0-A23)
The address inputs select the cells in the memory array to access during bus read
operations. During bus write operations they control the commands sent to the command
interface of the Program/Erase Controller.
Data input/output (DQ0-DQ15)
The data I/O output the data stored at the selected address during a bus read operation or
input a command or the data to be programmed during a bus write operation.
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is at V
mode. When Chip Enable is at V
impedance and the power consumption is reduced to the standby level.
Output Enable (G)
The Output Enable input controls data outputs during the bus read operation of the memory.
Write Enable (W)
The Write Enable input controls the bus write operation of the memory’s command interface.
The data and address inputs are latched on the rising edge of Chip Enable or Write Enable,
whichever occurs first.
Reset (RP)
The Reset input provides a hardware reset of the memory. When Reset is at V
memory is in reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset supply current I
the value of I
Register is reset. When Reset is at V
mode the device enters asynchronous read mode, however, a negative transition of Chip
Enable or Latch Enable is required to ensure valid data outputs.
Figure 1: Logic diagram
DD2.
After Reset all blocks are in the protected state and the Configuration
and
IH
Table 1: Signal names
the memory is deselected, the outputs are high
IH
DD2
, the device is in normal operation. Upon exiting reset
. Refer to
IL
and Reset is at V
Table 20: DC characteristics - currents
for a brief overview of the signals
IH
the device is in active
Signal descriptions
IL
, the
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for