XRT83VSH314ES Exar, XRT83VSH314ES Datasheet - Page 70

• Manufacturer Part Number: XRT83VSH314ES
• Description: Peripheral Drivers & Components - PCIs 14 CHT1/E1LIUSH LOW COST VERSION
• Manufacturer: Exar

Specifications of XRT83VSH314ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
CLOCK SELECT REGISTER
The input clock source is used to generate all the necessary clock references internally to the LIU. The
microprocessor timing is derived from a PLL output which is chosen by programming the Clock Select Bits in
register 0xE9h. Therefore, if the clock selection bits are being programmed, the frequency of the PLL output
will be adjusted accordingly. During this adjustment, it is important to "Not" write to any other bit location within
the same register while selecting the input/output clock frequency. For best results, register 0xE9h can be
broken down into two sub-registers with the MSB being bit D4 and the LSB being bits D[3:0] as shown in
Figure
N
F
Programming Examples:
Example 1 : Changing bits D[7:4]
If bit D4 is the only values within the register that will change in a WRITE process, the microprocessor only
needs to initiate ONE write operation.
Example 2 : Changing bits D[3:0]
If bits D[3:0] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 3 : Changing bits within the MSB and LSB
In this scenario, one must initiate TWO write operations such that the MSB and LSB do not change within ONE
write cycle. It is recommended that the MSB and LSB be treated as two independent sub-registers. One can
either change the clock selection bits D[3:0] (LSB) and then change bit D4 (MSB) on the SECOND write, or
vice-versa. No order or sequence is necessary.
OTE
IGURE
B
D7
D6
D5
D4
D3
D2
D1
D0
: Bits D[7:5] are reserved.
IT
36.
36. R
LCVCNT7
LCVCNT6
LCVCNT5
LCVCNT4
LCVCNT3
LCVCNT2
LCVCNT1
LCVCNT0
EGISTER
N
AME
0
T
X
ABLE
E9
D7
Line Code Violation Byte Contents
These bits contain the LCV counter contents of the Byte selected
by bit D2 in register 0xE6h for a given channel. The channel is
addressed by using bits D[3:0] in register 0xE5h. By default, the
contents contain the LSB, however no channel is selected..
H
Reserved,
S
48: M
UB
D6
R
EGISTERS
ICROPROCESSOR
MSB
D5
G
TCLKCNTL
LOBAL
D4
R
F
UNCTION
EGISTER
R
67
EGISTER
D3
(0
X
E8
Clock Selection Bits
0
X
H
E8
D2
)
H
B
IT
LSB
D1
D
ESCRIPTION
D0
Register
Type
R/W
(HW reset)
REV. 1.0.1
Default
Value
0
0
0
0
0
0
0
0