XRT83VSH314ES Exar, XRT83VSH314ES Datasheet - Page 42

• Manufacturer Part Number: XRT83VSH314ES
• Description: Peripheral Drivers & Components - PCIs 14 CHT1/E1LIUSH LOW COST VERSION
• Manufacturer: Exar

Specifications of XRT83VSH314ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
This test verifies the per-channel continuity from the Line Side of TIP and RING for both the transmitters and
receivers, through the transformers on the assembly and LIU. Inside the LIU, a MUX and Control logic using
TMS and TCK as reset and clock, successively connect each TIP and RING on the XRT83VSH314 side to two
Analog Test Pins, (ATP_TIP and ATP_RING). Simplified block and timing diagrams are shown in
and
Testing of each channel must be done in sequence. With a clock signal applied to TCK, Setting TMS to “0” will
begin the test sequence. On the falling edge of the 1st clock pulse after TMS is set to “0”, the sequence will
reset as shown in
TTIP_0 and TRING_0, respectively. On the falling edge of the 17th clock pulse the signal on ATP_TIP and
ATP_RING wiill be connected to RTIP_0 and RRING_0, respectively. After the 30th clock pulse TMS can be
returned to a “1” and all channels will return to their normal state.
Device side testing is implemented via the ATP_TIP and ATP_RING pins. The Line side Testing is done via the
Line Side Receive and Transmit TIP and RING connections.
Each channel of the device can be tested from the line side by doing the following:
1. Apply a differental 2Vpp, 1MHz signal to the Tx Line Side channel TIP and RING pins.
2. Measure the signal at the device ATP_TIP and ATP_RING pins.
3. If the voltage measured ATP_TTIP/TRING pins is 1Vpp±20%, your assembly is correct.
F
F
5.7
5.7.1
IGURE
IGURE
TCK
TMS
Figure
30. ATP
31. T
Analog Board Continuity Check
Transmitter TTIP and TRING Testing
31.
ATP_TIP
ATP_RING
TMS
TCK
IMING
1
Reset
TESTING BLOCK DIAGRAM
Figure 31
D
IAGRAM FOR
2
Tx0
XRT83VSH31
above. On the 2nd falling clock edge the signal on ATP_TIP and ATP_RING will be
XRT83SH314
Control Logic
3
Tx1
4
MU
ATP T
X
&
S
4
Tx2
ESTING
RRING_n
TRING_n
n = 0:13
RTIP_n
TTIP_n
15
Tx13
39
16
1:2
1:1
17
Rx0
18
Rx1
19
LINE SIDE Tx
Rx2
LINE SIDE
TRING
TTIP
RTIP
RRING
Rx
30
RX13
REV. 1.0.1
Figure 30