XRT83VSH314ES Exar, XRT83VSH314ES Datasheet - Page 33

• Manufacturer Part Number: XRT83VSH314ES
• Description: Peripheral Drivers & Components - PCIs 14 CHT1/E1LIUSH LOW COST VERSION
• Manufacturer: Exar

Specifications of XRT83VSH314ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

REV. 1.0.1
N
The driver monitor circuit is used to detect transmit driver failures by monitoring the activities at TTIP/TRING
outputs. Driver failure may be caused by a short circuit in the primary transformer or system problems at the
transmit inputs. If the transmitter of a channel has no output for more than 128 clock cycles, DMO goes "High"
until a valid transmit pulse is detected. If the DMO interrupt is enabled, the change in status of DMO will cause
the interrupt pin to go "Low". Once the status register is read, the interrupt pin will return "High" and the status
register will be reset (RUR).
The output stage of the transmit path generates standard return-to-zero (RZ) signals to the line interface for T1/
E1/J1 twisted pair or E1 coaxial cable.
impedance inside the LIU. This allows one bill of materials for all modes of operation reducing the number of
external components necessary in system design. The transmitter outputs only require one DC blocking
capacitor of 0.68
the appropriate channel register. A typical transmit interface is shown in
F
4.7
4.8
OTE
IGURE
: The same register bank (eight registers in total) holds the values for any given line length. In other words , the user
can not load all the desired values for all the line lengths into the device at one time. If the line length is changed, a
new code must be loaded into the register bank.
19. T
DMO (Digital Monitor Output)
Line Termination (TTIP/TRING)
YPICAL
µ
F. For redundancy applications (or simply to tri-state the transmitters), set TxTSEL to a "1" in
L
C
INE
133 - 266
266 - 399
399 - 525
525 - 655
ONNECTION
0 - 133
F
D
E1
EET
ISTANCE
Transmitter
Output
XRT83VSH314 LIU
Internal Impedance
D
IAGRAM
T
ABLE
T
T
RING
TIP
U
The physical interface is optimized by placing the terminating
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
24
29
30
34
39
2C
SING
11: T
1
I
YPICAL
NTERNAL
21
23
25
26
28
2A
C=0.68uF
30
2
ROM V
20
22
24
24
25
2A
One Bill of Materials
T
ERMINATION
3
ALUES
1:2
20
21
23
23
23
00
S
4
EGMENT
Figure
4C
4E
59
5F
59
00
Line Interface T1/E1/J1
5
#
19.
47
4A
40
50
50
00
6
44
47
48
48
48
00
XRT83VSH314
7
42
43
44
44
44
00
8