XRT83VSH314ES Exar, XRT83VSH314ES Datasheet - Page 21

• Manufacturer Part Number: XRT83VSH314ES
• Description: Peripheral Drivers & Components - PCIs 14 CHT1/E1LIUSH LOW COST VERSION
• Manufacturer: Exar

Specifications of XRT83VSH314ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

REV. 1.0.1
The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the
incoming data stream and outputs a clock that’s in phase with the incoming signal. This allows for multi-
channel T1/E1/J1 signals to arrive from different timing sources and remain independent. In the absence of an
incoming signal, RCLK maintains its timing by using the internal master clock as its reference. The recovered
data can be updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To
update data on the falling edge of RCLK, set RCLKE to "1" in the appropriate global register.
timing diagram of the receive data updated on the rising edge of RCLK.
receive data updated on the falling edge of RCLK. The timing specifications are shown in
3.2
RXTSEL
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Clock and Data Recovery
TERSEL1
x
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TERSEL0
x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
T
ABLE
RXRES1
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x
3: R
ECEIVE
18
RXRES0
T
ERMINATIONS
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x
240 Ω
240 Ω
240 Ω
240 Ω
210 Ω
210 Ω
210 Ω
210 Ω
150 Ω
150 Ω
150 Ω
150 Ω
R
R
∞
∞
∞
∞
ext
ext
Figure 6
100 Ω
120 Ω
172 Ω
204 Ω
108 Ω
240 Ω
192 Ω
232 Ω
280 Ω
300 Ω
412 Ω
150 Ω
600 Ω
110 Ω
116 Ω
75 Ω
R
is a timing diagram of the
∞
int
XRT83VSH314
Table
4.
Figure 5
T1/E1/J1
M
T1
E1
E1
T1
E1
E1
T1
E1
E1
T1
E1
E1
J1
J1
J1
J1
ODE
is a