XRT83VSH314ES Exar, XRT83VSH314ES Datasheet - Page 20

• Manufacturer Part Number: XRT83VSH314ES
• Description: Peripheral Drivers & Components - PCIs 14 CHT1/E1LIUSH LOW COST VERSION
• Manufacturer: Exar

Specifications of XRT83VSH314ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
The receive path of the XRT83VSH314 LIU consists of 14 independent T1/E1/J1 receivers. The following
section describes the complete receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs. A
simplified block diagram of the receive path is shown in
F
The input stage of the receive path accepts standard T1/E1/J1 twisted pair or E1 coaxial cable inputs through
RTIP and RRING. The physical interface is optimized by placing the terminating impedance inside the LIU.
This allows one bill of materials for all modes of operation reducing the number of external components
necessary in system design. The receive termination impedance (along with the transmit impedance) is
selected by programming TERSEL[1:0] to match the line impedance. Selecting the internal impedance is
shown in
The XRT83VSH314 has the ability to switch the internal termination to "High" impedance by programming
RxTSEL in the appropriate channel register. For internal termination, set RxTSEL to "1". By default, RxTSEL
is set to "0" ("High" impedance). For redundancy applications, a dedicated hardware pin (RxTSEL) is also
available to control the receive termination for all channels simultaneously. This hardware pin takes priority
over the register setting if RxTCNTL is set to "1" in the appropriate global register. If RxTCNTL is set to "0", the
state of this pin is ignored. See
F
3.0 RECEIVE PATH LINE INTERFACE
3.1
3.1.1
IGURE
IGURE
RPOS
RNEG
RCLK
3. S
4. T
Line Termination (RTIP/RRING)
Table
Internal Termination
YPICAL
IMPLIFIED
2.
HDB3/B8ZS
Internal Impedance
XRT83VSH314 LIU
Decoder
C
ONNECTION
B
LOCK
D
Receiver
IAGRAM OF THE
T
Figure 4
TERSEL[1:0]
D
Input
ABLE
Attenuator
Rx Jitter
IAGRAM
0h (00)
1h (01)
2h (10)
3h (11)
2: S
for a typical connection diagram using the internal termination.
R
R
U
RING
ELECTING THE
TIP
SING
R
ECEIVE
Clock & Data
I
Recovery
NTERNAL
17
Figure
P
I
ATH
NTERNAL
T
One Bill of Materials
ERMINATION
R
3.
ECEIVE
1:1
I
MPEDANCE
100 Ω
110 Ω
120 Ω
75 Ω
T
ERMINATION
Peak Detector
Line Interface T1/E1/J1
& Slicer
REV. 1.0.1
RTIP
RRING