XRT83VSH314ES Exar, XRT83VSH314ES Datasheet - Page 60

• Manufacturer Part Number: XRT83VSH314ES
• Description: Peripheral Drivers & Components - PCIs 14 CHT1/E1LIUSH LOW COST VERSION
• Manufacturer: Exar

Specifications of XRT83VSH314ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
N
OTE
B
: The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the
D7
D6
D5
D4
D3
D2
IT
interrupt pin.
Reserved
Reserved
LCV_OF
N
DMO
AISD
FLS
AME
T
ABLE
This Bit is Reserved
Digital Monitor Output
The digital monitor output is always active regardless if the inter-
rupt generation is disabled. This bit indicates the DMO activity. An
interrupt will not occur unless the DMOIE is set to "1" in the chan-
nel register 0x04h and GIE is set to "1" in the global register
0xE0h.
0 = No Alarm
1 = Transmit output driver has failures
FIFO Limit Status
The FIFO limit status is always active regardless if the interrupt
generation is disabled. This bit indicates whether the RD/WR
pointers are within 3-Bits. An interrupt will not occur unless the
FLSIE is set to "1" in the channel register 0x04h and GIE is set to
"1" in the global register 0xE0h.
0 = No Alarm
1 = RD/WR FIFO pointers are within ±3-Bits
Line Code Violation / Counter Overflow
This bit serves a dual purpose. By default, this bit monitors the line
code violation activity. However, if bit 7 in register 0xE5h is set to a
"1", this bit monitors the overflow status of the internal LCV
counter. An interrupt will not occur unless the LCV_OFIE is set to
"1" in the channel register 0x04h and GIE is set to "1" in the global
register 0xE0h.
0 = No Alarm
1 = A line code violation, bipolar violation, or excessive zeros has
occurred
This Bit is Reserved
Alarm Indication Signal Detection
The alarm indication signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the AIS
activity. An interrupt will not occur unless the AISIE is set to "1" in
the channel register 0x04h and GIE is set to "1" in the global regis-
ter 0xE0h.
0 = No Alarm
1 = An all ones signal is detected
29: M
ICROPROCESSOR
C
HANNEL
0-13 (0
F
UNCTION
R
57
EGISTER
X
05
H
-0
0
X
D5
X
05
H
H
)
B
IT
D
ESCRIPTION
Register
Type
RO
RO
RO
RO
RO
RO
(HW reset)
REV. 1.0.1
Default
Value
0
0
0
0
0
0