XRT83VSH314ES Exar, XRT83VSH314ES Datasheet - Page 68

• Manufacturer Part Number: XRT83VSH314ES
• Description: Peripheral Drivers & Components - PCIs 14 CHT1/E1LIUSH LOW COST VERSION
• Manufacturer: Exar

Specifications of XRT83VSH314ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83VSH314
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
D[7:5]
B
B
D4
D3
D2
D1
D0
D4
D3
IT
IT
allUPDATE LCV Counter Update for All Channels
Reserved
Reserved
LCVCH3
LCVCH2
LCVCH1
LCVCH0
allRST
N
N
AME
AME
T
T
ABLE
ABLE
This Register Bit is Not Used
Line Code Violation Counter Select
These bits are used to select which channel is to be addressed for
reading the contents in register 0xE8h. It is also used to address
the counter for a given channel when performing an update or
reset on a per channel basis. By default, Channel 0 is selected.
0000, 1111 = None
0001 = Channel 0
0010 = Channel 1
0011 = Channel 2
0100 = Channel 3
0101 = Channel 4
0110 = Channel 5
0111 = Channel 6
1000 = Channel 7
1001 = Channel 8
1010 = Channel 9
1011 = Channel 10
1100 = Channel 11
1101 = Channel 12
1110 = Channel 13
These Register Bits are Not Used
LCV Counter Reset for All Channels
This bit is used to reset all internal LCV counters to their default
state 0000h. This bit must be set to "1" for 1 µ S.
0 = Normal Operation
1 = Resets all Counters
This bit is used to latch the contents of all 14 counters into holding
registers so that the value of each counter can be read. The chan-
nel is addressed by using bits D[3:0] in register 0xE5h.
0 = Normal Operation
1 = Updates all Counters
45: M
46: M
ICROPROCESSOR
ICROPROCESSOR
G
G
LOBAL
LOBAL
R
F
R
F
UNCTION
UNCTION
EGISTER
EGISTER
R
R
65
EGISTER
EGISTER
(0
(0
X
X
E5
E6
0
0
X
X
H
H
E5
E6
)
)
H
H
B
B
IT
IT
D
D
ESCRIPTION
ESCRIPTION
Register
Register
Type
Type
R/W
R/W
R/W
R/W
R/W
(HW reset)
(HW reset)
REV. 1.0.1
Default
Default
Value
Value
0
0
0
0
0
0
0
0