DS26528GA4 Maxim Integrated, DS26528GA4 Datasheet - Page 258

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DS26528GA4

Manufacturer Part Number
DS26528GA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS26528GA4

Part # Aliases
90-26528-GA4
Table 12-3. Transmit AC Characteristics
(V
Figure
TCLK Period
TCLK Pulse Width
TSYSCLK Period
TSYSCLK Pulse Width
TSYNC or TSSYNCIO Setup to TCLK
or TSYSCLK falling
TSYNC or TSSYNCIO Pulse Width
TSSYNCIO Pulse Width (Notes 7, 8)
TSER, TSIG Setup to TCLK,
TSYSCLK Falling
TSER, TSIG Hold from TCLK,
TSYSCLK Falling
Delay TCLK to TCHBLK, TCHCLK,
TSYNC
Delay TSYSCLK to TCHCLK, TCHBLK
Delay TCLK to TTIP, TRING
Delay BPCLK to TSSYNCIO (Note 7)
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
DD
= 3.3V ±5%, T
12-11.)
The timing parameters in this table are guaranteed by design (GBD).
T1 Mode.
E1 Mode.
RSYSCLK = 1.544MHz.
RSYSCLK = 2.048MHz.
TSSYNCIO configured as an input (GTCR2.1 = 0).
TSSYNCIO configured as an output (GTCR2.1 = 1).
Varies depending on the frequency of BPCLK.
PARAMETER
A
= -40°C to +85°C.) (Note 1) (See
SYMBOL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PW
PW
CP
CH
CL
SP
SH
SU
SU
HD
D2
D3
D4
D5
SL
258 of 276
(Note 2)
(Note 3)
(Note 4)
(Note 5)
(Note 6)
CONDITIONS
Figure
12-8,
Figure
MIN
125
125
488
244
122
60
60
30
30
20
50
61
20
20
DS26528 Octal T1/E1/J1 Transceiver
12-9,
TYP
648
488
648
448
Figure
12-10, and
t
t
MAX
CH
SH
50
50
50
or
5
- 5
- 5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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