DS26528GA4 Maxim Integrated, DS26528GA4 Datasheet - Page 112
DS26528GA4
Manufacturer Part Number
DS26528GA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26528GNA4.pdf
(276 pages)
Specifications of DS26528GA4
Part # Aliases
90-26528-GA4
- Current page: 112 of 276
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 2: LOS Selection (LOSS). If this bit is set, the AL/RSIGF/FLOS pins can be driven with LIU loss. If reset, they
can be driven by framer LOS. The selection of whether to drive AL/RSIGF/FLOS pins with LOS (analog or digital)
or signalling freeze is controlled by GFCR.2. This selection affects all ports.
Bit 1: Transmit System Synchronization I/O Select (TSSYNCIOSEL). If this bit is set to a 1, the TSSYNCIO is
an 8kHz output synchronous to the BPCLK. This “frame pulse” can be used in conjunction with the backplane clock
to provide IBO signals for a system backplane. If this bit is reset, TSSYNCIO is an input. An 8kHz frame pulse is
required for transmit synchronization and IBO operation.
—
7
0
GTCR2
Global Transceiver Control Register 2
0F2h
—
6
0
—
5
0
112 of 276
—
0
4
—
3
0
LOSS
DS26528 Octal T1/E1/J1 Transceiver
2
0
TSSYNCIOSEL
1
0
—
0
0
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