DS26528GA4 Maxim Integrated, DS26528GA4 Datasheet - Page 128
DS26528GA4
Manufacturer Part Number
DS26528GA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26528GNA4.pdf
(276 pages)
Specifications of DS26528GA4
Part # Aliases
90-26528-GA4
- Current page: 128 of 276
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 4: Sa4 Change Detect Interrupt Mask (RSa4IM). This bit will enable the change detect interrupt for the Sa4
bits. Any change of state of the Sa4 bit will then generate an interrupt in RLS7.0 to indicate the change of state.
Bit 3: Sa5 Change Detect Interrupt Mask (RSa5IM). This bit will enable the change detect interrupt for the Sa5
bits. Any change of state of the Sa5 bit will then generate an interrupt in RLS7.0 to indicate the change of state.
Bit 2: Sa6 Change Detect Interrupt Mask (RSa6IM). This bit will enable the change detect interrupt for the Sa6
bits. Any change of state of the Sa6 bit will then generate an interrupt in RLS7.0 to indicate the change of state.
Bit 1: Sa7 Change Detect Interrupt Mask (RSa7IM). This bit will enable the change detect interrupt for the Sa7
bits. Any change of state of the Sa7 bit will then generate an interrupt in RLS7.0 to indicate the change of state.
Bit 0: Sa8 Change Detect Interrupt Mask (RSa8IM). This bit will enable the change detect interrupt for the Sa8
bits. Any change of state of the Sa8 bit will then generate an interrupt in RLS7.0 to indicate the change of state.
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
—
7
0
E1RSAIMR (E1 Mode Only)
Receive Sa-Bit Interrupt Mask Register
014h + (200h x n): where n = 0 to 7, for Ports 1 to 8
—
6
0
—
5
0
128 of 276
RSa4IM
4
0
RSa5IM
3
0
DS26528 Octal T1/E1/J1 Transceiver
RSa6IM
2
0
RSa7IM
1
0
RSa8IM
0
0
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