DS26528GA4 Maxim Integrated, DS26528GA4 Datasheet - Page 234
DS26528GA4
Manufacturer Part Number
DS26528GA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26528GNA4.pdf
(276 pages)
Specifications of DS26528GA4
Part # Aliases
90-26528-GA4
- Current page: 234 of 276
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 6: BERT Bit-Error-Detected Event (BBED).
Bit 5: BERT Bit Counter Overflow Event (BBCO).
Bit 4: BERT Error Counter Overflow Event (BECO).
Bit 3: BERT Receive All-Ones Condition (BRA1).
Bit 2: BERT Receive All-Zeros Condition (BRA0).
Bit 1: BERT Receive Loss of Synchronization Condition (BRLOS)
Bit 0: BERT in Synchronization Condition (BSYNC).
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled—interrupts on rising and falling edges
0 = interrupt masked
1 = interrupt enabled—interrupts on rising and falling edges
0 = interrupt masked
1 = interrupt enabled—interrupts on rising and falling edges
0 = interrupt masked
1 = interrupt enabled—interrupts on rising and falling edges
—
7
0
BSIM
BERT Status Interrupt Mask Register
110Fh + (10h x n): where n = 0 to 7, for Ports 1 to 8
BBED
6
0
BBCO
5
0
234 of 276
BECO
4
0
BRA1
3
0
DS26528 Octal T1/E1/J1 Transceiver
BRA0
2
0
BRLOS
1
0
BSYNC
0
0
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