DS26528GA4 Maxim Integrated, DS26528GA4 Datasheet - Page 168

• Manufacturer Part Number: DS26528GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26528GA4

• Part # Aliases: 90-26528-GA4

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: For E1 mode, see RIM3.
Bit 7: Loss of Receive Clock Condition Clear (LORCC).
Bit 6: Spare Code Detected Condition Clear (LSPC).
Bit 5: Loop-Down Code Detected Condition Clear (LDNC).
Bit 4: Loop-Up Code Detected Condition Clear (LUPC).
Bit 3: Loss of Receive Clock Condition Detect (LORCD).
Bit 2: Spare Code Detected Condition Detect (LSPD).
Bit 1: Loop-Down Code Detected Condition Detect (LDND).
Bit 0: Loop-Up Code Detected Condition Detect (LUPD).
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
LORCC
7
0
RIM3 (T1 Mode)
Receive Interrupt Mask Register 3
0A2h + (200h x n): where n = 0 to 7, for Ports 1 to 8
LSPC
6
0
LDNC
5
0
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LUPC
4
0
LORCD
3
0
DS26528 Octal T1/E1/J1 Transceiver
LSPD
2
0
LDND
1
0
LUPD
0
0