DS26528GA4 Maxim Integrated, DS26528GA4 Datasheet - Page 237

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DS26528GA4

Manufacturer Part Number
DS26528GA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS26528GA4

Part # Aliases
90-26528-GA4
Figure 10-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)
RCHBLK
RSYSCLK
RMSYNC
RCHCLK
RSYNC
RSYNC
RSER
RSIG
NOTE 1: RSER DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 ARE FORCED TO ONE.
NOTE 2: RSYNC IS IN THE OUTPUT MODE (RIOCR.2 = 0).
NOTE 3: RSYNC IS IN THE INPUT MODE (RIOCR.2 = 1).
NOTE 4: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.
NOTE 5: THE F-BIT POSITION IS PASSED THROUGH THE RECEIVE-SIDE ELASTIC STORE.
3
2
4
1
CHANNEL 31
A
CHANNEL 31
B
C/A D/B
LSB MSB
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CHANNEL 32
A
CHANNEL 32
B
C/A D/B
DS26528 Octal T1/E1/J1 Transceiver
LSB
CHANNEL 1
CHANNEL 1

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