DS26528GA4 Maxim Integrated, DS26528GA4 Datasheet - Page 205

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DS26528GA4

Manufacturer Part Number
DS26528GA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet

Specifications of DS26528GA4

Part # Aliases
90-26528-GA4
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 2: Transmit BERT Port Direction Control (TBPDIR).
Bit 1: Transmit BERT Port Framed/Unframed Select (TBPFUS).
Bit 0: Transmit BERT Port Enable (TBPEN).
0 = Normal (line) operation. Transmit BERT port sources data into the transmit path.
1 = System (backplane) operation. Transmit BERT port sources data into the receive path (RDATA). In this
mode the data out of the transmit BERT is muxed into the receive path at RDATA (the line side of the
elastic store).
0 = The transmit BERT will not clock data into the F-bit position (framed)
1 = The transmit BERT will clock data into the F-bit position (unframed)
0 = Transmit BERT port is not active
1 = Transmit BERT port is active
7
0
TXPC
Transmit Expansion Port Control Register
18Ah + (200h x n): where n = 0 to 7, for Ports 1 to 8
6
0
5
0
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4
0
3
0
DS26528 Octal T1/E1/J1 Transceiver
TBPDIR
2
0
TBPFUS
1
0
TBPEN
0
0

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