DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 7

• Manufacturer Part Number: DS26524GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26524GA4

• Part # Aliases: 90-26524-GA4

DS26524 Quad T1/E1/J1 Transceiver
LIST OF TABLES
Table 4-1. T1-Related Telecommunications Specifications ...................................................................................... 14
Table 4-2. E1-Related Telecommunications Specifications ...................................................................................... 15
Table 5-1. Time Slot Numbering Schemes................................................................................................................ 16
Table 7-1. Detailed Pin Descriptions ......................................................................................................................... 19
Table 8-1. Reset Functions........................................................................................................................................ 28
Table 8-2. Registers Related to the Elastic Store...................................................................................................... 31
Table 8-3. Elastic Store Delay After Initialization....................................................................................................... 32
Table 8-4. Registers Related to the IBO Multiplexer ................................................................................................. 34
Table 8-5. RSER Output Pin Definitions.................................................................................................................... 38
Table 8-6. RSIG Output Pin Definitions ..................................................................................................................... 38
Table 8-7. TSER Input Pin Definitions ....................................................................................................................... 39
Table 8-8. TSIG Input Pin Definitions ........................................................................................................................ 39
Table 8-9. RSYNC Input Pin Definitions .................................................................................................................... 39
Table 8-10. D4 Framing Mode................................................................................................................................... 42
Table 8-11. ESF Framing Mode ................................................................................................................................ 43
Table 8-12. SLC-96 Framing ..................................................................................................................................... 43
Table 8-13. E1 FAS/NFAS Framing .......................................................................................................................... 45
Table 8-14. Registers Related to Setting Up the Framer .......................................................................................... 46
Table 8-15. Registers Related to the Transmit Synchronizer.................................................................................... 47
Table 8-16. Registers Related to Signaling ............................................................................................................... 48
Table 8-17. Registers Related to SLC-96.................................................................................................................. 51
Table 8-18. Registers Related to T1 Transmit BOC.................................................................................................. 52
Table 8-19. Registers Related to T1 Receive BOC................................................................................................... 53
Table 8-20. Registers Related to T1 Transmit FDL................................................................................................... 53
Table 8-21. Registers Related to T1 Receive FDL.................................................................................................... 54
Table 8-22. Registers Related to E1 Data Link ......................................................................................................... 54
Table 8-23. Registers Related to Maintenance and Alarms...................................................................................... 56
Table 8-24. T1 Alarm Criteria .................................................................................................................................... 58
Table 8-25. T1 Line Code Violation Counting Options .............................................................................................. 59
Table 8-26. E1 Line Code Violation Counting Options .............................................................................................. 60
Table 8-27. T1 Path Code Violation Counting Arrangements ................................................................................... 60
Table 8-28. T1 Frames Out of Sync Counting Arrangements ................................................................................... 60
Table 8-29. Registers Related to DS0 Monitoring ..................................................................................................... 61
Table 8-30. Registers Related to T1 In-Band Loop Code Generator ........................................................................ 63
Table 8-31. Registers Related to T1 In-Band Loop Code Detection ......................................................................... 64
Table 8-32. Registers Related to Framer Payload Loopbacks.................................................................................. 65
Table 8-33. Registers Related to the HDLC .............................................................................................................. 66
Table 8-34. Recommended Supply Decoupling ........................................................................................................ 73
Table 8-35. Registers Related to Control of DS26524 LIU ....................................................................................... 74
Table 8-36. Telecommunications Specification Compliance for DS26524 Transmitters .......................................... 75
Table 8-37. Transformer Specifications..................................................................................................................... 75
Table 8-38. ANSI T1.231, ITU-T G.775, and ETS 300 233 Loss Criteria Specifications .......................................... 79
Table 8-39. Jitter Attenuator Standards Compliance................................................................................................. 81
Table 8-40. Registers Related to BERT Configure, Control, and Status................................................................... 84
Table 9-1. Register Address Ranges (in Hex)........................................................................................................... 86
Table 9-2. Global Register List .................................................................................................................................. 88
Table 9-3. Framer Register List ................................................................................................................................. 89
Table 9-4. LIU Register List ....................................................................................................................................... 96
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