DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 243

• Manufacturer Part Number: DS26524GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26524GA4

• Part # Aliases: 90-26524-GA4

10.3
Figure 10-15. E1 Receive-Side Timing
Figure 10-16. E1 Receive-Side Boundary Timing (Elastic Store Disabled)
RCHBLK
E1 Receiver Functional Timing Diagrams
RFSYNC
RCHCLK
RFSYNC
RSYNC
RSYNC
RSYNC
FRAME#
RSER
RCLK
RSIG
NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.
NOTE 2: SHOWN IS A RNAF FRAME BOUNDARY.
NOTE 3. RSIG NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1.
1
2
NOTE 1: RSYNC IN FRAME MODE (RIOCR.0 = 0).
NOTE 2: RSYNC IN MULTIFRAME MODE (RIOCR.0 = 1).
NOTE 3: THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME.
1
1
CHANNEL 32
CHANNEL 32
2
A
B
3
C
4
LSB
D
5
Si
6
1
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7
A Sa4 Sa5 Sa6 Sa7 Sa8
8
CHANNEL 1
CHANNEL 1
9
Note 3
10
11
12 13
MSB
14
CHANNEL 2
CHANNEL 2
15
A
16
B
1