DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 250
DS26524GA4
Manufacturer Part Number
DS26524GA4
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS26524GA4.pdf
(273 pages)
Specifications of DS26524GA4
Part # Aliases
90-26524-GA4
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12.
Unless otherwise noted, all timing numbers assume 20pF test load on output signals, 40pF test load on bus
signals.
12.1
Table 12-1. AC Characteristics—Microprocessor Bus Timing
(V
Figure
Setup Time for A[12:0] Valid to CSB
Active
Setup Time for CSB Active to Either RDB,
or WRB Active
Delay Time from Either RDB or DSB
Active to D[7:0] Valid
Hold Time from Either RDB or WRB
Inactive to CSB Inactive
Hold Time from CSB or RDB or DSB
Inactive to D[7:0] Tri-State
Wait Time from WRB Active to Latch Data
Data Setup Time to WRB Inactive
Data Hold Time from WRB Inactive
Address Hold from WRB Inactive
Write Access to Subsequent Write/Read
Access Delay Time
Note 1:
Note 2:
DD
= 3.3V ±5%, T
12-3, and
AC TIMING CHARACTERISTICS
Microprocessor Bus AC Characteristics
The timing parameters in this table are guaranteed by design (GBD).
If supplying a 1.544MHz MCLK, the FREQSEL bit must be set to meet this timing.
PARAMETER
Figure
A
= -40°C to +85°C for DS26524GN.) (Note 1) (See
12-4.)
SYMBOL
t10
t1
t2
t3
t4
t5
t6
t7
t8
t9
250 of 273
(Note 2)
(Note 2)
CONDITIONS
DS26524 Quad T1/E1/J1 Transceiver
Figure
MIN
40
10
80
0
0
0
5
2
0
12-1,
TYP
Figure
MAX
125
20
12-2,
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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