DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 2

• Manufacturer Part Number: DS26524GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26524GA4

• Part # Aliases: 90-26524-GA4

1.
2.
3.
4.
5.
6.
7.
8.
1.1
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
7.1
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.2.1
8.4.1
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.9.6
8.9.7
8.9.8
8.9.9
8.9.10
8.9.11
DETAILED DESCRIPTION.................................................................................................9
FEATURE HIGHLIGHTS ..................................................................................................10
APPLICATIONS ...............................................................................................................13
SPECIFICATIONS COMPLIANCE ...................................................................................14
ACRONYMS AND GLOSSARY .......................................................................................16
BLOCK DIAGRAMS.........................................................................................................17
PIN DESCRIPTIONS ........................................................................................................19
FUNCTIONAL DESCRIPTION .........................................................................................26
M
G
L
C
J
F
S
HDLC C
T
C
P
P
C
R
I
G
P
D
S
F
NITIALIZATION AND
ITTER
INE
RAMER
EST AND
RAMERS
YSTEM
IN
ROCESSOR
ER
YSTEM
LOCK
ONTROL
LOCK
ESETS AND
EVICE
ENERAL
LOBAL
AJOR
F
Backplane Clock Generation ............................................................................................................... 26
Example Device Initialization Sequence .............................................................................................. 29
-P
Elastic Stores ....................................................................................................................................... 31
IBO Multiplexer..................................................................................................................................... 34
H.100 (CT Bus) Compatibility .............................................................................................................. 40
Receive and Transmit Channel Blocking Registers............................................................................. 41
Transmit Fractional Support (Gapped Clock Mode) ............................................................................ 41
Receive Fractional Support (Gapped Clock Mode) ............................................................................. 41
T1 Framing........................................................................................................................................... 42
E1 Framing........................................................................................................................................... 45
T1 Transmit Synchronizer .................................................................................................................... 47
Signaling .............................................................................................................................................. 48
T1 Data Link......................................................................................................................................... 52
E1 Data Link......................................................................................................................................... 54
Maintenance and Alarms ..................................................................................................................... 55
E1 Automatic Alarm Generation .......................................................................................................... 58
Error-Count Registers .......................................................................................................................... 59
DS0 Monitoring Function...................................................................................................................... 61
Transmit Per-Channel Idle Code Insertion........................................................................................... 62
I
UNCTIONAL
NTERFACE
ORT
A
S
S
O
I
/F
R
NTERRUPTS
I
ONTROLLERS
B
TTENUATOR
YNTHESIZER
TRUCTURE
PERATING
NTERFACE
......................................................................................................................................10
......................................................................................................................................42
D
P
ESOURCES
ACKPLANE
ORMATTER
R
ORT
IAGNOSTICS
ESOURCES
I
P
NTERFACE
OWER
............................................................................................................................10
............................................................................................................................12
D
ESCRIPTION
C
.......................................................................................................................26
M
......................................................................................................................11
-D
.....................................................................................................................10
.....................................................................................................................29
ONFIGURATION
I
....................................................................................................................10
....................................................................................................................10
....................................................................................................................29
NTERFACE
ODES
...................................................................................................................12
OWN
................................................................................................................12
................................................................................................................26
................................................................................................................29
.............................................................................................................9
M
ODES
......................................................................................................19
TABLE OF CONTENTS
...................................................................................................31
..............................................................................................28
..............................................................................................29
2 of 273