DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 245

• Manufacturer Part Number: DS26524GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26524GA4

• Part # Aliases: 90-26524-GA4

10.4
Figure 10-19. E1 Transmit-Side Timing
Figure 10-20. E1 Transmit-Side Boundary Timing (Elastic Store Disabled)
E1 Transmitter Functional Timing Diagrams
FRAME#
TSYNC
TCHBLK
TSYNC
TCHCLK
TSSYNC
TSYNC
TSYNC
NOTE 1: TSYNC IN FRAME MODE (TIOCR.0 = 0).
NOTE 2: TSYNC IN MULTIFRAME MODE (TIOCR.0 = 1).
NOTE 3: THIS DIAGRAM ASSUMES BOTH THE CAS MF AND THE CRC-4 MF BEGIN WITH THE TAF FRAME.
TSER
TCLK
NOTE 1: TSYNC IN THE OUTPUT MODE (TIOCR.2 = 1).
NOTE 2: TSYNC IN THE INPUT MODE (TIOCR.2 = 0).
NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2.
NOTE 4: THE SIGNALING DATA AT TSIG DURING CHANNEL 1 IS NORMALLY OVERWRITTEN IN THE TRANSMIT
FORMATTER WITH THE CAS MF ALIGNMENT NIBBLE (0000).
NOTE 5: SHOWN IS A TNAF FRAME BOUNDARY.
TSIG
2
1
1
2
3
14 15 16
LSB
D
Si
1
1
2
A Sa4 Sa5 Sa6 Sa7 Sa8
3
CHANNEL 1
4
CHANNEL 1
5
6
7
8
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9 10
MSB
11 12
13 14 15 16 1
CHANNEL 2
CHANNEL 2
A
B
2
C
3
LSB MSB
4
D
5
6
7
8
9 10