DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 3

• Manufacturer Part Number: DS26524GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26524GA4

• Part # Aliases: 90-26524-GA4

9.
10.
11.
12.
13.
8.10
8.11
8.12
9.1
9.2
9.3
9.4
9.5
9.6
10.1
10.2
10.3
10.4
11.1
11.2
12.1
12.2
12.3
13.1
8.9.12
8.9.13
8.9.14
8.9.15
8.9.16
8.9.17
8.10.1
8.10.2
8.11.1
8.11.2
8.11.3
8.11.4
8.11.5
8.12.1
8.12.2
9.1.1
9.1.2
9.1.3
9.2.1
9.2.2
9.2.3
9.2.4
9.4.1
9.4.2
13.1.1
13.1.2
13.1.3
13.1.4
DEVICE REGISTERS .......................................................................................................86
FUNCTIONAL TIMING ...................................................................................................233
OPERATING PARAMETERS.........................................................................................248
AC TIMING CHARACTERISTICS ..................................................................................250
JTAG BOUNDARY SCAN AND TEST ACCESS PORT ................................................261
R
R
G
F
LIU R
BERT R
RAMER
EGISTER
EGISTER
LOBAL
HDLC C
L
B
T1 R
T1 T
E1 R
E1 T
T
L
M
JTAG I
S
TAP C
INE
INE
HERMAL
IT
YSTEM
ICROPROCESSOR
Receive Per-Channel Idle Code Insertion............................................................................................ 62
Per-Channel Loopback ........................................................................................................................ 62
E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only) ................................................................... 62
T1 Programmable In-Band Loop Code Generator............................................................................... 63
T1 Programmable In-Band Loop Code Detection................................................................................ 64
Framer Payload Loopbacks ................................................................................................................. 65
Receive HDLC Controller..................................................................................................................... 66
Transmit HDLC Controller.................................................................................................................... 69
LIU Operation....................................................................................................................................... 74
Transmitter ........................................................................................................................................... 75
Receiver ............................................................................................................................................... 78
Jitter Attenuator.................................................................................................................................... 81
LIU Loopbacks ..................................................................................................................................... 82
BERT Repetitive Pattern Set ............................................................................................................... 85
BERT Error Counter............................................................................................................................. 85
Global Register List.............................................................................................................................. 88
Framer Register List............................................................................................................................. 89
LIU and BERT Register List................................................................................................................. 96
Global Register Bit Map ....................................................................................................................... 97
Framer Register Bit Map ...................................................................................................................... 98
LIU Register Bit Map .......................................................................................................................... 106
BERT Register Bit Map ...................................................................................................................... 106
Receive Register Definitions.............................................................................................................. 122
Transmit Register Definitions............................................................................................................. 181
Test-Logic-Reset................................................................................................................................ 262
Run-Test-Idle ..................................................................................................................................... 262
Select-DR-Scan ................................................................................................................................. 262
Capture-DR ........................................................................................................................................ 262
-E
EGISTER
RANSMITTER
I
RANSMITTER
I
ECEIVER
ECEIVER
RROR
NTERFACE
NTERFACE
R
EGISTER
R
ONTROLLER
NTERFACE
EGISTER
L
B
EGISTER
ONTROLLERS
C
ISTINGS
C
IT
LOCK
-R
HARACTERISTICS
M
D
ATE
F
F
APS
EFINITIONS
D
UNCTIONAL
UNCTIONAL
AC C
U
C
D
EFINITIONS
D
F
F
T
......................................................................................................................86
......................................................................................................................97
T
NITS
HARACTERISTICS
EFINITIONS
EFINITIONS
S
UNCTIONAL
UNCTIONAL
EST
B
IMING
TATE
US
HARACTERISTICS
................................................................................................................66
(LIU
(BERT) F
AC C
.........................................................................................................216
.........................................................................................................259
M
T
T
S
.....................................................................................................225
ACHINE
IMING
....................................................................................................249
IMING
)....................................................................................................71
..................................................................................................107
HARACTERISTICS
.................................................................................................122
T
T
IMING
IMING
UNCTION
D
D
..........................................................................................249
.........................................................................................262
IAGRAMS
IAGRAMS
D
D
....................................................................................260
3 of 273
IAGRAMS
IAGRAMS
................................................................................84
..........................................................................233
..........................................................................243
........................................................................250
....................................................................238
....................................................................245