DS26524GA4 Maxim Integrated, DS26524GA4 Datasheet - Page 40

• Manufacturer Part Number: DS26524GA4
• Description: Network Controller & Processor ICs
• Manufacturer: Maxim Integrated

Specifications of DS26524GA4

• Part # Aliases: 90-26524-GA4

8.8.3
The registers used for controlling the H.100 backplane are
The H.100 (or CT bus) is a synchronous, bit-serial, TDM transport bus operating at 8.192MHz. The H.100 standard
also allows compatibility modes to operate at 2.048MHz, 4.096MHz, or 8.192MHz. The control bit H100EN
(RIOCR.5), when combined with RSYNCINV and TSSYNCINV, allows the DS26524 to accept a CT bus-
compatible frame-sync signal (CT_FRAME) at the RSYNC and TSSYNCIO (input mode) inputs.
The following rules apply to the H100EN control bit.
Figure 8-6. RSYNC Input in H.100 (CT Bus) Mode
1) The H100EN bit controls the sampling point for the RSYNC (input mode) and TSSYNCIO (input mode)
2) The H100EN bit would always be used in conjunction with the receive and transmit elastic store buffers.
3) The H100EN bit would typically be used with 8.192MHz IBO mode, but could also be used with 4.096MHz
4) The H100EN bit in RIOCR controls both RSYNC and TSSYNCIO (i.e., there is no separate control bit for
5) The H100EN bit does not invert the expected signal; RSYNCINV (RIOCR) and TSSYNCINV (TIOCR) must
H.100 (CT Bus) Compatibility
only. The RSYNC output and other sync signals are not affected.
IBO mode or 2.048MHz backplane operation.
the TSSYNCIO).
be set high to invert the inbound sync signals.
RSYSCLK
RSYNC
RSYNC
RSER
NOTE 1: RSYNC INPUT MODE IN NORMAL OPERATION.
NOTE 2: RSYNC INPUT MODE, H100EN = 1 AND RSYNCINV = 1.
NOTE 3: t
2
1
BC
(BIT CELL TIME) = 122ns (typ). t
BIT 8
BC
= 244ns or 488ns ALSO ACCEPTABLE.
t
BIT 1
BC
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3
RIOCR
and TIOCR.
BIT 2