AT89LP51ED2-20AU Atmel, AT89LP51ED2-20AU Datasheet - Page 9

• Manufacturer Part Number: AT89LP51ED2-20AU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20AU

• Rohs: yes
• Core: 8051
• Processor Series: AT89x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 160

2.2.2
3714A–MICRO–7/11
Software Options
Table 2-1.
Table 2-2
level. These can be changed by the application software but are set to their default values upon
any reset. Most peripherals also have multiple configuration bits that are not listed here.
Table 2-2.
Fuse Name
Clock Source A
Clock Source B
Oscillator Select
X2 Mode
Start-up Time
Compatibility Mode
XRAM Configuration
Bootloader Jump Bit
On-Chip Debug Enable
In-System Programming Enable
User Signature Programming Enable
Default Port State
Low Power Mode
Bit(s)
PxM0.y
PxM1.y
CKRL
TPS
ALES
EXRAM
WS
XSTK
EEE
ENBOOT
1-0
3-0
lists some important software configuration bits that affect operation at the system
SFR Location
P0M0, P0M1, P1M0, P1M1,
P2M0, P2M1, P3M0, P3M1,
P4M0, P4M1
CKRL
CLKREG.7-4
AUXR.0
AUXR.1
AUXR.6-5
AUXR1.4
EECON.1
AUXR1.5
User Configuration Fuses
Important Software Configuration Bits
AT89LP51RD2/ED2/ID2 Preliminary
Description
Selects between the High Speed Crystal Oscillator, Low Power
Crystal Oscillator, External Clock on XTAL1A or Internal RC Oscillator
for the source of the system clock when oscillator A is selected.
Selects between the 32 kHzCrystal Oscillator, External Clock on
XTAL1B or Internal RC Oscillator for the source of the system clock
when oscillator B is selected (AT89LP51ID2 Only).
Selects whether oscillator A or B is enabled to boot the device.
(AT89LP51ID2 Only)
Selects the default state of whether the clock source is divided by two
(X1) or not (X2) to generate the system clock.
Selects time-out delay for the POR/BOD/PWD wake-up period.
Configures the CPU in 12-clock compatibility or single-cycle fast
execution mode.
Configures if access to on-chip memories that are mapped to the
external data memory address space is enabled/disabled by default.
Enables or disables the on-ship bootloader.
Enables or disables On-Chip Debug. OCD must be enabled prior to
using an in-circuit debugger with the device.
Enables or disables In-System Programming.
Enables or disables programming of User Signature array.
Configures the default port state as input-only mode (tristated) or
quasi-bidirectional mode (weakly pulled high).
Enables or disables power reduction features for lower system
frequencies.
Description
Configures the I/O mode of Port x Pin y to be one of input-only, quasi-
bidirectional, push-pull output or open-drain. The default state is
controlled by the Default Port State fuse above
Selects the division ratio between the oscillator and the system clock
Selects the division ratio between the system clock and the timers
Enables/disables toggling of ALE
Enables/disables access to on-chip memories that are mapped to the
external data memory address space
Selects the number of wait states when accessing external data
memory
Configures the hardware stack to be in RAM or extra RAM
Enables/disables access to the on-chip EEPROM
Enables/disables access to the on-chip Flash API
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