AT89LP51ED2-20AU Atmel, AT89LP51ED2-20AU Datasheet - Page 185

• Manufacturer Part Number: AT89LP51ED2-20AU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20AU

• Rohs: yes
• Core: 8051
• Processor Series: AT89x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 160

23. On-Chip Debug System
23.1
3714A–MICRO–7/11
Physical Interface
The AT89LP51RD2/ED2/ID2 On-Chip Debug (OCD) System uses a two-wire serial interface to
control program flow; read, modify, and write the system state; and program the nonvolatile
memory. The OCD System has the following features:
The On-Chip Debug System uses a two-wire synchronous serial interface to establish communi-
cation between the target device and the controlling emulator system. The OCD interface is
enabled by clearing the OCD Enable Fuse. The OCD device connections are shown in
23-1. When OCD is enabled, the RST port pin is configured as an input for the Debug Clock
(DCL). P4.3 is a bi-directional data line for the Debug Data (DDA).
When designing a system where On-Chip Debug will be used, the following observations must
be considered for correct operation:
Figure 23-1. AT89LP51RD2/ED2/ID2 On-Chip Debug Connections
• Complete program flow control
• Read-Modify-Write access to all internal SFRs and data memories
• Four hardware program address breakpoints
• Four program/data address breakpoints configurable in 2 maskable pairs.
• Unlimited program software breakpoints using BREAK instruction
• Break on change in program memory flow
• Break on stack overflow/underflow
• Break on Watchdog overflow
• Break on reset
• Non-intrusive operation
• Programming of nonvolatile memory
• RST cannot be connected directly to V
• All external reset sources must be removed.
• OCD is shipped disabled from the factory. A device programmer is required to enable this
• Enabling OCD disables the RST input and thereby disables the In-System Programming
connected to RST must be removed.
fuse before debugging can occur.
interface (ISP). ISP can only be re-entered by holding RST active at power-up. The
bootloader remains active and has priority over the OCD system.
GND or VDD
AT89LP51RD2/ED2/ID2 Preliminary
DCL
AT89LP51RD2/ED2/ID2
DD
RST
POL
GND
or GND and any external capacitors or supervisors
VDD
P4.3
DDA
Figure
185