AT89LP51ED2-20AU Atmel, AT89LP51ED2-20AU Datasheet - Page 59

• Manufacturer Part Number: AT89LP51ED2-20AU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20AU

• Rohs: yes
• Core: 8051
• Processor Series: AT89x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 160

8.2.2
8.3
3714A–MICRO–7/11
Reducing Power Consumption
Reset Recovery from Power-down
Figure 8-2.
The wake-up from Power-down through an external reset is similar to the interrupt with
PWDEX = “1”. At the rising edge of RST, Power-down is exited, the oscillator is restarted, and
an internal timer begins counting as shown in
propagate to the CPU until after the timer has timed out. The time-out period is controlled by the
Start-up Timer Fuses. (See
clock cycle internal reset is generated when the internal clock restarts. Otherwise, the device will
remain in reset until RST is brought low.
Figure 8-3.
Several possibilities need consideration when trying to reduce the power consumption in an
8051-based system.
• Idle or Power-down mode should be used as often as possible with interrupts waking up the
• All un-needed peripheral functions should be disabled
• The System Clock Prescaler can scale down the operating frequency during periods of low
• The ALE output can be disabled by setting AO in AUXR, thereby also reducing EMI
• Write to the EEPROM by page instead of by byte to limit the number of write cycles
• For AT89LP51ID2, switch the system clock from a high power oscillator like XTALA to a lower
system to handle specific tasks
demand (See
power oscillator like the internal 8 MHz oscillator during periods when frequency accuracy is
not as important.
Internal
Internal
Internal
XTAL1
XTAL1
Reset
Clock
Clock
PWD
PWD
INT1
RST
Interrupt Recovery from Power-down (PWDEX = 0)
Reset Recovery from Power-down (POL = 1)
“System Clock Prescaler” on page
Table 7-1 on page
AT89LP51RD2/ED2/ID2 Preliminary
Figure
54). If RST returns low before the time-out, a two
t SUT
49.)
8-3. The internal clock will not be allowed to
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