AT89LP51ED2-20AU Atmel, AT89LP51ED2-20AU Datasheet - Page 18

• Manufacturer Part Number: AT89LP51ED2-20AU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20AU

• Rohs: yes
• Core: 8051
• Processor Series: AT89x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 160

18
AT89LP51RD2/ED2/ID2 Preliminary
Figure 3-7
a 16-bit linear address. Port 0 serves as a multiplexed address/data bus to the RAM. The
Address Latch Enable strobe (ALE) is used to latch the lower address byte into an external reg-
ister so that Port 0 can be freed for data input/output. Port 2 provides the upper address byte
throughout the operation. The MOVX @DPTR instructions use Linear Address mode.
Figure 3-7.
Figure 3-8
an 8-bit paged address. Port 0 serves as a multiplexed address/data bus to the RAM. The ALE
strobe is used to latch the address byte into an external register so that Port 0 can be freed for
data input/output. The Port 2 I/O lines (or other ports) can provide control lines to page the mem-
ory; however, this operation is not handled automatically by hardware. The software application
must change the Port 2 register when appropriate to access different pages. The MOVX @Ri
instructions use Paged Address mode.
Figure 3-8.
Note that prior to using the external memory interface, WR (P3.6) and RD (P3.7) must be config-
ured as outputs. See
automatically to push-pull output mode when outputting address or data and P0 is automatically
tristated when inputting data regardless of the port configuration. The Port 0 configuration will
determine the idle state of Port 0 when not accessing the external memory.
Figure 3-9
respectively. The address on P0 and P2 is stable at the falling edge of ALE. The idle state of
ALE is controlled by DISALE (AUXR.0). When DISALE = 0 the ALE toggles at a constant rate
when not accessing external memory. When DISALE = 1 the ALE is weakly pulled high. DISALE
must be one in order to use P4.4 as a general-purpose I/O. The WS bits in AUXR can extended
the RD and WR strobes by 1, 2 or 3 cycles as shown in Figures 3-13, 3-14 and 3-15. If a longer
shows a hardware configuration for accessing 256-byte blocks of external RAM using
shows a hardware configuration for accessing up to 64K bytes of external RAM using
and
External Data Memory 16-bit Linear Address Mode
External Data Memory 8-bit Paged Address Mode
Figure 3-10
Section 12.1 “Port Configuration” on page
P1
show examples of external data memory write and read cycles,
P1
RD
WR
RD
WR
AT89LP
AT89LP
P3
P3
P2
ALE
ALE
P0
P2
P0
I/O
LATCH
LATCH
PAGE
BITS
DATA
DATA
EXTERNAL
EXTERNAL
WE
MEMORY
MEMORY
WE
ADDR
ADDR
DATA
DATA
71. P0 and P2 are configured
OE
OE
3714A–MICRO–7/11